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PSoC 5, 3 & 1 MCU

AlVa_264671
New Contributor II

Hi

I'm implementing  analogs inputs con Vddio  @ 3.3v  in very noisy environment from EMI and surges.

According to PSoC 5LP data sheet the absolute maximum rating es Vddio+ 0.5 V.

I found ESD diode like ESDM1131  from OM Semiconductors.

VRWM is 3.3 V - VBR max @ IT 1ma is 6v.

The clamping voltage Typ.  is  5.5 V or 7 V  according to the IEC 61000-4-2   level 2 .

Ipp is 4A @t 8/20 us pulse.

I don't have much experience working with this type of protection and the clamping voltage and Ipp current are my doubt.

Is there some PSoC 5LP parameter which let me know if there's some tolerance spec. related with the power that one pin in

above mentioned condition can withstand?

My question is focused on the possibility of use this diode or better some TVS diode..

Thank you.

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1 Solution
Vasanth
Moderator
Moderator

Hi,

The absolute maximum voltage allowed on PSoC GPIO pins is 0.5 V above the GPIO pin supply or 0.5 V below ground.  If there is any chance of the input voltage to exceed this, it is recommended to protect the PSoC device by using a series resistor and Schottky diode arrangement as shown in the following diagram.

The diodes D_1 and D_2 are low forward drop Schottky diodes such as the NSR05F20NXT5G Schottky Barrier Diode from ON Semiconductor. See the datasheet at https://www.onsemi.com/pub/Collateral/NSR05F20.PDF

A R_3 resistor value of 100 Ω will keep the voltage on the GPIO pin below ± 0.4 V (over VDD/below Gnd) for Vinput values up to ± 50 V. Therefore, the PSoC device will remain unaffected because it can stand voltages up to ± 0.5 V (over VDD/below Gnd) on its GPIO pins.

Best Regards,
Vasanth

View solution in original post

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1 Reply
Vasanth
Moderator
Moderator

Hi,

The absolute maximum voltage allowed on PSoC GPIO pins is 0.5 V above the GPIO pin supply or 0.5 V below ground.  If there is any chance of the input voltage to exceed this, it is recommended to protect the PSoC device by using a series resistor and Schottky diode arrangement as shown in the following diagram.

The diodes D_1 and D_2 are low forward drop Schottky diodes such as the NSR05F20NXT5G Schottky Barrier Diode from ON Semiconductor. See the datasheet at https://www.onsemi.com/pub/Collateral/NSR05F20.PDF

A R_3 resistor value of 100 Ω will keep the voltage on the GPIO pin below ± 0.4 V (over VDD/below Gnd) for Vinput values up to ± 50 V. Therefore, the PSoC device will remain unaffected because it can stand voltages up to ± 0.5 V (over VDD/below Gnd) on its GPIO pins.

Best Regards,
Vasanth

View solution in original post

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