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Hi all,
I'd like to confirm the monitoring voltage of Power On Reset of PSoC4(CY8C4247LTI-L475).
It is described as follows in TRM(PSoC 4200L Family Architecture TRM).
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9.3.1 Power-On-Reset (POR)
POR circuits provide a reset pulse during the initial power ramp.
POR circuits monitor VCCD voltage.
13.1.1 Power-on Reset
Power-on reset is provided for system reset at power-up.
POR holds the device in reset until the supply voltage, VDDD, is according to the datasheet specification.
The POR activates automatically at power-up.
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Which is POR monitoring, VCCD or VDDD?
Best regards.
Yasu
Solved! Go to Solution.
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VCCD is used for POR monitoring.
- VDDD is Power supply for both analog and digital sections (where there is no VDDA pin)
- VCCD is Regulated digital supply (1.8 V ±5%)
As the additional information, please refer to the PSoC 4200 L datasheet
https://www.cypress.com/file/222206/download
Section "Unregulated External Supply" and "Regulated External Supply".
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VCCD is used for POR monitoring.
- VDDD is Power supply for both analog and digital sections (where there is no VDDA pin)
- VCCD is Regulated digital supply (1.8 V ±5%)
As the additional information, please refer to the PSoC 4200 L datasheet
https://www.cypress.com/file/222206/download
Section "Unregulated External Supply" and "Regulated External Supply".
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Hello TakashiM_61-san,
Thank you for your update.
I'd like to confirm POR release conditions.
I think that POR is released when VCCD exceeds the threshold and the internal oscillator stabilizes.
Q2)
I think the threshold of VCCD is 1.71V(1.8V - 5%).
Is my idea correct?
Q3)
How long does it take for the internal oscillator to stabilize after VCCD exceeds the threshold?
Best regards,
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Hello,
Apologize for late response...
Answer 2) If you say POR, you should consider VDDD. Then, it would be Min value of VDDD.
Note that there are 2 cases with regular enabled / internal unregurated supply.
PSoC® 4: PSoC 4200L Datasheet
https://www.cypress.com/file/222206/download
Answer 3) According to Figure 4-2. Timing Diagram of Entering Test Mode, CY8C4xxx, CYBLxxxx Programming Specifications (https://www.cypress.com/file/409516/download)
the IMO stabilization would be happened before "boot code" executed.
So, it would be approximately less that 1ms.
thanks.