PSoC™ 4 Forum Discussions
I would like to be able to send a command to the psoc that will switch the SWD pins back from GPIO mode to SWD mode. I know there is a setting for this in the system tab but I do not see any obvious way to set this during runtime. Is it possible?
Show LessHello,
I am using PSoC4 L-Series-Pioneer Kit (CY8KIT-046). After I added the UART (non SCB) component to my current project I start getting this build error:
cydsfit.exe -.appdatapath "C:\Users\NikolayPruss\AppData\Local\Cypress Semiconductor\PSoC Creator\4.2" -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p C:\Users\NikolayPruss\WORK\stellar-beam\psoc4\TxSlat\MasterPSoC.cydsn\MasterPSoC.cyprj -d CY8C4248BZI-L489 -s C:\Users\NikolayPruss\WORK\stellar-beam\psoc4\TxSlat\MasterPSoC.cydsn\Generated_Source\PSoC4 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE
Elaborating Design...
HDL Generation...
Synthesis...
Tech Mapping...
ADD: pft.M0040: information: The following 2 pin(s) will be assigned a location by the fitter: \I2CM:scl(0)\, \I2CM:sda(0)\
Error: mpr.M0014: Resource limit: Maximum number of Status Cells exceeded (max=8, needed=9). (App=cydsfit)
Dependency Generation...
Cleanup...
Error: fit.M0050: The fitter aborted due to errors, please address all errors and rebuild. (App=cydsfit)
So my project contains USB component, two SPI master componets (non SCB), one I2C component (SCB), 5 individual pins (three of them are LEDs) and now UART (non SCB). I noticed that if I make the UART component as SCB, then the project builds fine. This fact is confusing because I thought that the SCB resources are much more limitted than non SCB. Could anybody explain the problem that I have here?
Thank you!
Nikolay
Show LessI am currently working on a small BLE-epaper interface with the CYBLE-212020 module.
SPI-Communication and different sleep-modes work fine, But now I am struggling with the extended power saving modes.
You can find the core application in the attached zip-bundle.
I measured the current with a UNI-T Multimeter in the CY8CKIT--042-BLE-Pioneer kit with the CYBLE-212020-Eval board.
Main clock is 24MHz and current consumption in active mode is around 11mA. During the first 10s, the high speed advertising interrupt causes a current consumption of around 3mA. The next 20s it drops down to below 2mA for the slow advertising.
But after that it rises to 12mA again for some seconds and then only drops to 4-5mA, when the device should be in stop mode.
I expect that the current consumption in deep sleep is not accurate, because of the high frequency between sleep and active, but for the stop mode it should be precise.
When I use a custom PCB for the CYBLE-212020 module, The values are a little bit lower, but still in stop mode the current is nearly up to 2mA, with no additional pheripheral hardware around. No LEDs, no epaper, nothing.
Did I forget anything before entering Stop mode?
Or what is the reason for that high current consumption?
Thanks
Andreas
Show LessHi,
I'm having a problem on a CY8CKIT-049-42XX with the UDB FIFO's.
I have core code that writes into the F0 FIFO (checking before that the FIFO is not full). There is verilog code that has a DP that reads the F0 value into A0 when the FIFO_EMPTY flag is low.
I initialise the FIFO by writing 0x03, then 0x00 to the AUX Ctrl register for that DP, and following this the flags to the bus and the block indicate that the FIFO is empty.
However, when I write a sequence of bytes into F0 and examine A0 after each write, it is clear that the FIFO still contains data immediately after initialisation that is read out before the data that I have written in.
That is to say, the AUX_REG writes appear to clear the external full/empty flags, but the internal FIFO read/write pointers do not appear to be reset correctly.
Typically I seem to read out 3 "other" values before I see the values that I am writing in.
I appear to see the problem both on UDB00 and UDB03 (I haven't tried the other two).
Any thoughts on the problem?
Regards
Ziggles
Show LessHi.
I would like to use the clock as an external clock input instead of a crystal.
Looking at the data sheet, the description of the 16th pin (XTAL24I) in the PSoC4 BLE 4.2 Pin List (QFN Package) is given as 24-MHz crystal or external clock input. The external clock is called CMOS input level only.
So I did not use XTAL24O pin 17 and connected CMOS signal to pin 16 only. But it did not work.
If you look at the CLK settings in the PSoC Creator tool, there are P0.4, P2.7, and P5.1 pin settings in EXTCLK. Do you need to connect CMOS signals to these pins? I do not know ..
I thought it would work if I just put the CMOS signal on the XTAL24I pin.
I would appreciate it if you let me know what went wrong.
Thank you.
Data Sheet --> http://www.cypress.com/file/213801/download http://www.cypress.com/file/213801/download
Show Less4.1 update one compiles fine, but upgrading to 4.2 breaks the build.
The complaint about preventing usage of special purposes is strange, since those special purposes are not being used.
cydsfit.exe -.appdatapath "C:\Users\fdever\AppData\Local\Cypress Semiconductor\PSoC Creator\4.2" -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p C:\Users\fdever\dual_array\firmware\proj\Test_Dual_Valve.cydsn\Test_Dual_Valve.cyprj -d CYBLE-214015-01 -s C:\Users\fdever\dual_array\firmware\proj\Test_Dual_Valve.cydsn\Generated_Source\PSoC4 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE
Elaborating Design...
ADD: sdb.M0065: information: Analog terminal "ADC_1M.analog_0" on TopDesign is unconnected.
* C:\Users\fdever\dual_array\firmware\proj\Test_Dual_Valve.cydsn\TopDesign\TopDesign.cysch (Signal: Net_243)
* C:\Users\fdever\dual_array\firmware\proj\Test_Dual_Valve.cydsn\TopDesign\TopDesign.cysch (Shape_1872.1)
* C:\Users\fdever\dual_array\firmware\proj\Test_Dual_Valve.cydsn\TopDesign\TopDesign.cysch (Shape_465)
* C:\Users\fdever\dual_array\firmware\proj\Test_Dual_Valve.cydsn\TopDesign\TopDesign.cysch (Shape_471)
* C:\Users\fdever\dual_array\firmware\proj\Test_Dual_Valve.cydsn\TopDesign\TopDesign.cysch (Shape_472)
HDL Generation...
Synthesis...
Tech Mapping...
Info: plm.M0038: The pin named \SDI:PIN_SDI12(0)\ at location P3[3] prevents usage of special purposes: SCB[0].uart_cts. (App=cydsfit)
Info: plm.M0038: The pin named \SDI:PIN_SDI12(0)\ at location P3[3] prevents usage of special purposes: SARMUX[0].pads[3]. (App=cydsfit)
Analog Placement...
Analog Routing...
Error: apr.M0003: Unable to find a solution for the analog routing. (App=cydsfit)
Dependency Generation...
Cleanup...
Error: fit.M0050: The fitter aborted due to errors, please address all errors and rebuild. (App=cydsfit)
Show LessI've got Rx reception only of an array of the 40 bytes, but I cannot Tx the answering array of 60-bytes consistently.
So far I've got the following Rx code to work without Tx'ing, now get just a few mcu<-->mcu transfers(1 pac reception and one pac Tx'ing) and then pgm locks up while Rx or Tx.
I've been workings on this problem tens of hours trying to disambiguate the spec sheet to write correct code!
The mostly likely cause of my problems is that I'm not coding handling of the interrupts properly, causing the pgm to hang.
I
My goal:
Receive 40-bytes from a PIC MCU which is a mixture of binary data and cmds. The Cy then processes these bytes and sends back an answering array also of 60 bytes.
The PIC MCU initiates each session every .2-Sec,
The Cy should answer back with Tx'ing 60-bytes immediately after processing the received data, and just once within .2 Sec, then it waits for the next packet of 48 bytes.
I know the PIC is Tx'ing and working perfectly, verified RS232 for proper timing/data on my digital storage scope.
I cannot seem to get the information on how to do this properly from the SCB UART datasheet(SCB Ver. 3.20) it offers many possible options, but almost no guidance on what API's to use and I cannot seem to disambiguate the when, where, how, why or why not to use them.
My confusion is immense, even though I have been successfully coding MCU's for ten's of years(mostly PIC lately.)
Googled the web and Cy websites, nothing but the most vague and elementary examples, but only way too simple, not well-explained and non-robust code found.
Working for a living as a programmer means that "A word too wise is not sufficient!"
As a result my coding is cut and try coding..I am desperately attempting to hack my code to work!
//-----------------------------
I have SCB config'd Tx and Rx buffer size set to 62 and 41 bytes respectively.
The only interrupt I have selected for TX is UART_DONE.
For receive, only the default Rx FIFO not empty
I am using only internal interrupts and my INT_UART interrupt handler has the alias UA and handles both Rx and Tx interrupts.
I have initialized and started the UART interrupt handler correctly since it does work intermittently,
//Before main()
CY_ISR_PROTO (ISR_UART); //in prototypes list (doesn't seem to make any difference if it omitted.
static unsigned char Rx[56], Tx[62], *tp=Tx;
static unsigned int Pacs;
volatile unsigned char Findit, Sent, HmS5, rbyt, k, erx;
int main()
{
start: //----------------------- start -----------------------
if(newbyte)
{ if(HmS5>4) //every 5 hundred milliseconds
{ Cy2p();
Sent=0; //clear to send next packet to PIC
HmS5=0;
led_Write(0); //lights up active low to indicate pac reception/TX activity
}
if((Rx[2]==0xAA)&&(Rx[4]==0xAA)&&(Rx[6]==0xAA)) //redundant check for a correct order of bytes in array received
{ Pacs++; //diagnostic to count successful full pacs received
}
else
{ erx++; //diagnostic ot count error pacs received
}
wa: if(Display!=Ready) goto wa;
strcpy(bp,"P= ");Value=Pacs;ParseNum();strcat(bp,np);
if(erx)
{ strcat(bp," E= ");Value=erx;ParseNum();strcat(bp,np);
}
FillBuf();Display=Displaying;
newbyte=0;
}
goto start;
void ISR_UART()
{
int32 source; //var holds states of all UA interrupt flags states
//When newbyte is set, this ISR handles the TX interrupt, otherwise the Rx
if(newbyte==1) .// flag set indicates a full packet of 48-bytes has been received and pauses reception until reset by main processing.
{ goto HandleTx;
}
Getit:
source = UA_GetRxInterruptSource(); // Returns the status of RX interrupt source that caused interrupt event
// Checkr "RX FIFO not empty" interrupt
if(UA_INTR_RX_NOT_EMPTY & source)
{
k = UA_UartGetByte();
if(rbyt==0)Rx[0]=k;
// Attempt to Clear UART "RX FIFO not empty interrupt"
UA_ClearRxInterruptSource(UA_INTR_RX_NOT_EMPTY); //Does not clear if FIFO has more bytes
if(FindSt==0)
{
if( (rbyt==0)&&(k==0xAA) )//possible start of a pac. Pac start bytes are all 0xAA start bytes are bytes 0,2,4,6 or array received
{ FindSt=1; // found possible start of a stream
rbyt=1;
Rx[rbyt]=k;
}
else
{ goto StartEr;
}
}
if(FindSt)
{ if( (rbyt==2)||(rbyt==4)||(rbyt==6) ) //using the first four even bytes set always to 0xAA to detect correct start of a Rx or Tx stream.
{ if(k != 0xAA) goto StartEr; //bad start detected
}
}
if(rbyt) //stream has started to being received
{ Rx[rbyt]=k;
rbyt++;
if(rbyt<40) //40 bytes for now is expected from PIC
{ goto Getit; //check for any more bytes in FIFO
}
else //assume a pac of 40 bytes 0-39 has been received
{
FindSt=0;
rbyt=0;
newbyte=1;
goto Clrit;
led_Write(1);
}
}
else
{
StartEr:
rbyt=0;
FindSt=0;
goto Getit;
}
}
HandleTx:
if(Sent==1) //Flag indicating that a packet has started/finished sending a packet of bytes to PIC by a call to Cy2p()
{ source = UA_GetTxInterruptSource();
if(UA_INTR_TX_UART_DONE & source)
{ UA_ClearTxInterruptSource(UA_INTR_TX_UART_DONE); //Does not clear if FIFO has more bytes
UA_ClearPendingInt();
}
}
Clrit:;
//UA_ClearPendingInt();
UA_rx_ClearInterrupt();
}
//Tx data setup routine
void Cy2p()
{ // code not shown updating values of Tx[ ] array of 60 bytes, then
if(Sent==0) //A received pac received, now Cy answers:
{
UA_SpiUartClearTxBuffer();
UA_SpiUartPutArray(tp,60u);
Sent=1;
HmS5=0;
}
}
Show LessI'm working on a very simple application with logic operators, I assign 3 inputs and 2 outputs, when I build the system it gives message:
Unable to place component "\Comp_0:cy_psoc4_lpcomp_1\". Either the design is bigger than this chip can handle, or the design is over-constrained and there are not enough resources to satisfy the constraints.
I suspect it may be a Psoc creator 3.2 software issue but not 100% sure.
I have chip: CY8CKIT-049-42xx PSOC 4
How can I fix this issue?
Show LessHi All,
BLE -CY8C4247LQI-BL483
PSOC4 creator
=> I have created one custom profile application and able to receive string from cypress app to device.Now my problem is I am able to receive the string for only one time after the connection established.If I want to send another string immediately I have to disconnect the existing connection and have to reconnect again.I am not able to understand why it was like that.Please can any one tell if I am missing anything to configure in the BLE settings.
=> One more problem is with my miniprog3 debugger I am not able to start debug session,previously I have done debugging now suddenly I am not able to do debug.
Regards
srikanth.
Show LessI am using a cyble212020. The device has a single button that is used to put the micro in deepsleep and wakeup. The button generates an interrupt to wakeup the micro. The code has a timer counter and an isr routine to handle timer functions and led controls. About 1 in 10 times after wakeup from deepsleep the code will hang in isr_1. Using timer_1_clearinterrupt to clear in the isr and in the wakeup code. Tried many things to get it running but no luck so far. Thanks
Show Less