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PSoC™ 4 Forum Discussions

LR61_4569216
PSoC™ 4
How to lock the configure of the MBR serial chip for reading only? Show More
YuMa_1534086
PSoC™ 4
Hello Cypress. Q1)When Tx clock source setting is “Auto”, how does CSX select it? Below is my understanding.Is my understanding correct? ============... Show More
jaro_4538801
PSoC™ 4
I'm trying to make a luxometer using PSOC 5LP CY8C5888LTI-LP097 with this code#include <project.h>#include <stdio.h>#include <math.h>int main(){    ui... Show More
UlMo_4589691
PSoC™ 4
SDA(P0.5) and SCL(P3.0). The raspberry detects another I2C. Here is the code. I am using PSoC 4.#include <project.h>uint8 bufSize;uint8 readBuffer[] =... Show More
Doorknob
PSoC™ 4
I am doing a project that uses 5 capsense buttons to operate a locking mechanism in my project. I m having issues that when i power up the unit by pla... Show More
GrWa_2302706
PSoC™ 4
HiThere is a problem if CAN host sends large amount of data, CY8C4147 cannot receive data.Does cypress have CAN software filter ? Thanks.BRGrace Show More
GiBA_1125241
PSoC™ 4
As described in Em_EEPROM 2.0 datasheet, I have an Em_EEPROM whose storage is at a fixed address,and it is working very well.When i add a bootloadable... Show More
GrWa_2302706
PSoC™ 4
Hi May I know how to define a const in the fixed flash address ?Thanks.BRGrace Show More
user_284076
PSoC™ 4
Hi,Can we implement similar functionality mentioned here https://community.cypress.com/docs/DOC-14244​ for PSOC3/5LP in PSOC4. Can we control GPIO fro... Show More
YaKu_1055906
PSoC™ 4
Hello All,As shown in the figure below, SARADC block diagram in  PSoC4 Architecture TRM is not displayed correctly.Could you tell me the correct figur... Show More
Forum Information

PSoC™ 4

PSoC™ 4 - Arm®-based Forum, discusses the low-power Cortex®-M0 and Cortex®-M0+ cores, CapSense®, and Bluetooth® Low Energy