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PSoC 4 MCU

Anonymous
Not applicable

Hi

   

Newby here. I am using a PSoc4200 (CY84245AXI-483). I have an ADC setup with a 5v reference (VDDA). I can only get 11 bits of resolution out of the ADC and I cannot seem to find anything in the datasheet to suggest that I cannot get 12 bits. What am I doing wrong or do I only get 11 bits from a 12bit ADC.

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8 Replies
Bob_Marlowe
Expert II

Can you post your complete project, so that we all can have a look at all of your settings? To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.

   

 

   

Bob

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Anonymous
Not applicable

Bob

   

That might be a problem as the design is not for public domain. How can we do this without me infringing somehow.

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Bob_Marlowe
Expert II

Reduce the (copy of the) project to the ADC issue. How you know it is 11 bit?

   

 

   

Bob

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Anonymous
Not applicable

I only get a count of 2047. With 12 bit it should at least go to 40xx.

   

The mv result is near 5v.

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Bob_Marlowe
Expert II

Another choice could be to create a "Support Case" (Top of this Page: Design Support -> Create a Support Case) to get in contact with Cypress directly. They keep your project secret, but it takes usually a bit more time.

   

 

   

Bob

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Bob_Marlowe
Expert II

Configuration set to +-values which would result in 12 bits?

   

 

   

Bob

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Anonymous
Not applicable

Hi Bob

   

Thanks for the help. I did log a case and the help was very quick and impressive. It was a setup issues as to be expected but not one that I would have been able to sort out by myself.

   

This is the response form them.

   


Yes you are right in your observation. The reason is that the ADC is actually a differential ADC, with half of its range occurring when the negative input is greater than the positive input. With your configuration(the Single ended negative input is "Vss"), the negative half of the range is never used. You may refer to the "Single ended result format" section in the SAR ADC component datasheet. Based on this, you can choose the following set of options: Vref = VDDA/2 (bypass, if required) Single ended negative input = Vref Single Ended Result format = Unsigned to achieve your requirement (of 0-VDDA range with entire 12-bits of resolution in this range). We understand this may appear a bit confusing, compared to the straight-forward single-ended configuration we typically would expect. But these settings are required because the ADC is actually a differential ADC, with half of its range occurring when the negative input is greater than the positive input. But the above mentioned settings make the differential (by architecture) ADC to appear as a single-ended 0-VDDA with all 12-bits of resolution in that range.
 

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Bob_Marlowe
Expert II

Thank you, Marius; for keeping us informed!

   

 

   

Bob

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