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PSoC 4 MCU

user_520646
New Contributor

The datasheet states that the DC resistance of the S/H input is max. 2.2kOhm.

Does this mean that the DC-load is actually 2.2Kohm or is this resistance just

in series with the S/H capacitor thus providing a much higher DC input resistance

after the signal has settled?

This parameter is important in order to estimate the gain-loss due to the built-in

output resistance of the connected external buffer-amplifier (this design)

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1 Solution
Vasanth
Moderator
Moderator

Hello Jorgen,

This image will be be self explanatory and should be able to help you with selecting the acquisition time.

pastedImage_0.png

you can check the architectural TRM ADC section http://www.cypress.com/file/126171/download . From the image you cans see that the DC resistance is due to the routing path.

The actual input impedance you see from the ADC will be higher than this. It is the routing resistance till the sampling capacitor. The actual resistance due to the sampling capacitor will be some where around  1/(sample rate * 6.4pF).

Best Regards,

VSRS

View solution in original post

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1 Reply
Vasanth
Moderator
Moderator

Hello Jorgen,

This image will be be self explanatory and should be able to help you with selecting the acquisition time.

pastedImage_0.png

you can check the architectural TRM ADC section http://www.cypress.com/file/126171/download . From the image you cans see that the DC resistance is due to the routing path.

The actual input impedance you see from the ADC will be higher than this. It is the routing resistance till the sampling capacitor. The actual resistance due to the sampling capacitor will be some where around  1/(sample rate * 6.4pF).

Best Regards,

VSRS

View solution in original post

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