Nor Flash Forum Discussions
Hi,
The memory capacity and die size of the below two model numbers are different.
Is there a difference in EMS performance such as Radiated electromagnetic field test (G-TEM cell) between these two types of ICs?
MPN:
S25FL256SAGMFBG00
S25FL512SAGMFI010
Best Regards,
Naoaki Morimoto
Show LessHello,
I am trying to communicate with S25HL512T NOR Flash with FTDI. Initially I am trying with single SPI mode. In the below snap I am trying to write the value to volatile configuration register 1 and reading back the configuration register 1, but not able to read the value what I written in Conf_reg 1.
With Regards,
Vijay KS
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I'm looking for the power consumptions of the nor flash modue. I have not been able to find a full TDS on this part.
Hi ,
I am using S25FL128L SPI flash memory in Single bit mode.
Reading of the register SR1, SR2, CR1, CR2, CR3 and UID seems to work, because all register have their default value.
But when I try to write some data to the flash I have problems. The first command of a write operation is the WRE (0x06) command. After sending the WRE command I read SR1 and check the WEL bit. I read the SR1 serval times, but this bit never goes high.
Can you please help me find the cause of this?
Thank you
Show LessHi,
We are considering replacing S25FL128SAG with S25FL128SDP.
Is it possible for S25FL128SDP to operate at S25FL128SAG's Fast Read maximum frequency of 133 MHz?
Are there any other points to note?
Best Regards,
Kumada
Show LessHi
Can you suggest where to download the REACH report? I have declaration already.
Thanks,
Hi!
I am using an example program from Xilinx to access the S25FL256SAGBHI20 flash memory and write some data at location 0xEA6000. For this, I have created an FPGA design with a Microblaze and the AXI SPI IP core. I am attaching the C code for the Microblaze that controls the flash memory access but here is the short version:
The XSpi_Transfer function accesses the flash registers over the AXI QSPI IP core.
#define INTEL_COMMAND_RANDOM_READ 0x03 /* Random read command */
#define INTEL_COMMAND_PAGEPROGRAM_WRITE 0x02 /* Page Program command */
#define INTEL_COMMAND_WRITE_ENABLE 0x06 /* Write Enable command */
#define INTEL_COMMAND_SECTOR_ERASE 0xD8 /* Sector Erase command */
#define INTEL_COMMAND_BULK_ERASE 0xC7 /* Bulk Erase command */
#define INTEL_COMMAND_STATUSREG_READ 0x05 /* Status read command */
#define INTEL_COMMAND_STATUSREG_WRITE 0x01 /* Status write command */
#define INTEL_READ_WRITE_EXTRA_BYTES 4 /* Read/Write extra bytes */
#define INTEL_WRITE_ENABLE_BYTES 1 /* Write Enable bytes */
#define INTEL_SECTOR_ERASE_BYTES 4 /* Sector erase extra bytes */
#define INTEL_BULK_ERASE_BYTES 1 /* Bulk erase extra bytes */
#define INTEL_STATUS_READ_BYTES 2 /* Status read bytes count */
#define INTEL_STATUS_WRITE_BYTES 2 /* Status write bytes count */
#define INTEL_FLASH_SR_IS_READY_MASK 0x01 /* Ready mask */
#define INTEL_DISABLE_PROTECTION_ALL 0x00
#define INTEL_FLASH_PAGE_SIZE 256
// Write enable
XSpi_Transfer(SpiPtr, INTEL_COMMAND_WRITE_ENABLE, NULL,
INTEL_WRITE_ENABLE_BYTES);
//Check if flash busy
XSpi_Transfer(SpiPtr, INTEL_COMMAND_STATUSREG_READ, ReadBuffer,
INTEL_STATUS_READ_BYTES);
StatusReg = ReadBuffer[1];
if((StatusReg & INTEL_FLASH_SR_IS_READY_MASK) == 0) {
break;
}
// Disable protection
WriteBuffer[BYTE1] = INTEL_COMMAND_STATUSREG_WRITE;
WriteBuffer[BYTE2] = INTEL_DISABLE_PROTECTION_ALL;
XSpi_Transfer(SpiPtr, WriteBuffer, NULL,
INTEL_STATUS_WRITE_BYTES);
// Write data to flash memory define in "Address"
WriteBuffer[BYTE1] = INTEL_COMMAND_PAGEPROGRAM_WRITE;
WriteBuffer[BYTE2] = (u8) ((Address+INTEL_FLASH_PAGE_SIZE) >> 16);
WriteBuffer[BYTE3] = (u8) ((Address+INTEL_FLASH_PAGE_SIZE) >> 8);
WriteBuffer[BYTE4] = (u8) (Address+INTEL_FLASH_PAGE_SIZE);
XSpi_Transfer(SpiPtr, WriteBuffer, NULL,
(INTEL_FLASH_PAGE_SIZE + INTEL_READ_WRITE_EXTRA_BYTES));
The writing of data works, because I can also read it back after power cycling the FPGA, the problem is just, that my FPGA design doesn’t boot any more. I have to program it new, every single time I power cycle it. I flash the FPGA file starting from memory 0x0 so the two memory regions should not overlap.
Any suggestion as why this doesnt work will be very welcome!
KR,
Aida
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Hi,
- I have S25FL064L Chip connected to Altera MAX II FPGA.
- My objective is to write a VHDL module to read/write words from/to the S25FL064L.
- I tried simulating the provided model S25FL064L - VERILOG (cypress.com) with Cypress's testbench, however, I cannot make sense of the resulting waveform; SI is giving HIGH IMPEDANCE upon receiving READ CMD 0x03 from the stimulating testbench's signals.
Is there anything I should configure before I read/write in this example testbench model?
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Hello:
I am migrating a design from S25FL127S to S25HL512T NOR flash. Couple of questions / issues:
- Is the data interface any different in the QSPI mode?
- How do I get a complete datasheet with the interface information? I have applied for the "early access" program and not received any response.
- Is there a separate data interface document?
I am trying to work on this today and I am disappointed that I cannot find any data interface information on the S25HLT devices on the web.
Thanks for your help !!!
Steve D
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