Nor Flash Forum Discussions
Hi All,
We are using OSPI NOR Flash S28HS512TGABHM013 in our product. It would be great if you can share compatible driver for Linux-5.10.35 version.
Hardware Platform: i.MX8QM
Best Regards
Babu A
Show LessHello everybody!
Recently I was doing some hacky/fancy tests of flash chip behavior between different manufacturers when it is used not *exactly* how it was intended 😉 I was changing configuration of external memory controller in my MCU to drive WE# line low or high during reading operation (used for example for chips with byte lane selection etc.) and I've encountered something strange which I couldn't find in the S29AL016J datasheet.
In other flash chip manufacturers (pin-to-pin comp. + same timings and control) when I try to perform read operation ("uint16_t test = *(uint16_t*)(FLASH_BASE);") everything works correctly, i.e. data is exposed on data lines if WE# line is driven high, and data lines are kept low if WE# line is driven low.
In S29AL016J it doesn't matter if MCU drives WE# line low or high during reading, chip drives data lines anyway!
It looks like some flash chip's internal state machine checks if address set on address lines is "special" one (0x555 etc.) and if not, it executes read operation and exposes data on data lines.
Could anybody confirm it?
Some snippet code looks like that:
//set EMC to drive WE# line low during reading
//EMC_cfg_we(FALSE);
//set EMC to drive WE# line high during reading
EMC_cfg_we(TRUE);
while(1)
{
uint8_t test = ( *( Uint16 * )(0x80000000L)) & 0xFF;
uart_putc(test);
delay_ms(500);
}
I have few identical PCBs with same MCU, only flash chip is different.
I would really appreciate for any explanation!
BR
Adam
Show LessDear all:
It seems some errors in S79FS01GS Datasheet
In chapter "Ordering Information" , what it described is S25FS series
In Packages description, there is sentence confict between FAB024 and ZSA024
Please help confirm and update correct datasheet,thanks
Show LessWe are planning on using S25FL256SAGNFI003 in a new PCB design we are doing. However, I was not able to find if the exposed pad should be connected electrically or left isolated as only a thermal pad.
Could you help identify how to electrically connect the exposed pad shown below?
(exposed pad shown):
Thanks,
-Nate
Show LessDear support and community member
Cypress S25FL256L-LAGMFM000
We've done a lot of test on this topic. While we are able to Erase (4K) with (0x20), Write (0x02), Read (0x48 or 0x03) security regions, we can't seem to make command 0x44 (Security Erase), or 0x42 (Security Write) working.
We are confident about SPI controller and the SPI master, since all other commands so far seems working perfectly. And as long as we change 0x44 to 0x20, 0x42 to 0x02, erase and write all work. But We don't want 4K erase.
Security Erase 0x44 command after sending SR1NV shows not WIP, so it is ready. And there is no error indicating in SR2V.
None of the security regions are locked, since we can do 4K erase, and program easily.
I can walkaround this issue by always doing 4K erase instead of 256-byte security erase for now. But we prefer to understand what is causing the trouble.
Please comment.
Thanks,
Show LessDear Support,
Good day,
Please help to check why the x ray is different , first one is 20+ , second one is 21+ .
Please help to share any PCN if there's available related to changes made. Thanks
PCBA layout have change. Please refer to photo.
Show Less
Dear Team,
It is mentioned in the datasheet that, S25FL256SAGMFI001 part is with EHPLC, SO/WSON footprint and S25FL256SAGMFAG00 is with EHPLC, SO footprint with RESET#.
So, what is the actual difference between these two parts?
If S25FL256SAGMFAG00 part is coming with RESET#, then does that mean S25FL256SAGMFI001 part won't be having RESET#?
Can you please explain the difference between the mentioned two parts.
Thanks,
Harish I I
Show Less