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Nor Flash

Anonymous
Not applicable

Hi there,

could you give me some consideration on the layout of the S70FL01GS Flash? I would like to use this flash in QSPI mode. In fact, I am going to use two of these ICs - one on the Top and another on the Bottom layers. From the datasheet I could see that there is no convenient pin swapping feature (such as in the DDRs), which is a bummer. Are there any consideration that I should keep in mind as to the Layout of the two Flash ICs?

Also, I have found this article http://www.cypress.com/file/217366/download​​, and I have a few questions regarding its content:

- It says that I have to keep CLK trace 50 Ohm char. impedance. My uC doesn't have 50 Ohm on the output of the QSPI pins (at least nothing is mentioned in the Datasheet). Will it help then to keep it 50 Ohm if I don't even know what is on the output of my SPI CLK pin (impedance-wise)?

- Do I really have to keep all the traces the same length, as critical as 3 mm? (It's just that the QSPI speed is not that high...)

Anyway, any suggestions will be appreciated!

Kind Regards,

Den

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1 Solution
Anonymous
Not applicable

Hello Den,

Q) Do I really have to keep all the traces the same length, as critical as 3 mm?

A) Yes it is important that the I/O traces are routed such that they have identical lengths, within ~ 3 mm, to assure equivalent propagation delays. To assure reliable data transfers for all configurations it is important that the propagation delays for the clock trace and all data traces are identical.

Q) Will it help then to keep it 50 Ohm if I don't even know what is on the output of my SPI CLK pin (impedance-wise)?

A) Yes clock trace should have 50 ohm char impedance.

Thanks,

Krishna.

View solution in original post

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3 Replies
Anonymous
Not applicable

Hello Den,

Q) Do I really have to keep all the traces the same length, as critical as 3 mm?

A) Yes it is important that the I/O traces are routed such that they have identical lengths, within ~ 3 mm, to assure equivalent propagation delays. To assure reliable data transfers for all configurations it is important that the propagation delays for the clock trace and all data traces are identical.

Q) Will it help then to keep it 50 Ohm if I don't even know what is on the output of my SPI CLK pin (impedance-wise)?

A) Yes clock trace should have 50 ohm char impedance.

Thanks,

Krishna.

View solution in original post

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Anonymous
Not applicable

Hi Krishna,

ok, well that confirms what is in your article, not like I really doubted it, I just wanted an explanation why, especially about the 50 Ohm impedance, since If my pin has different impedance than 50 Ohm, even if you tune it to 50 Ohm a 1000 times, there will be reflection... hence - weird. But nonetheless, fine. Any other suggestions about the layout?

Kind Regards,

Den

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Anonymous
Not applicable

Hello Den,

No other suggestions about the lay out.

Thanks,

Krishna.

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