- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
Several I2C EEPROMs have a software reset sequence.
When the power-on EEPROM falls into an incorrect state (due to excessive bus noise, etc.)
or when the microcontroller is reset during communication.
In such a case, the serial EEPROM device can reset correctly by sending the following sequence.
• Start bit
• 9-bit "1" clock
• Start bit
• Stop bit
Is it possible to perform a software reset also in FRAM of Cypress?
Best Regards,
Naoaki Morimoto
Solved! Go to Solution.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I kindly request you to refer to one of our Application Note from this link below:
http://www.cypress.com/file/195656/download
As mentioned in the Application Note, in Table 4, page 6, I2C F-RAM does not require this feature.
However if implemented, it will have no impact on the device operation.
Thanks,
Nada
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I kindly request you to refer to one of our Application Note from this link below:
http://www.cypress.com/file/195656/download
As mentioned in the Application Note, in Table 4, page 6, I2C F-RAM does not require this feature.
However if implemented, it will have no impact on the device operation.
Thanks,
Nada