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Non Volatile RAM (F-RAM & NVSRAM)

coli_4707641
New Contributor

Dear Sirs,

  I have just started to use these FRAM memories. My test software for writing and reading is working 99% of the time.Occasionally I get a corrupted read immediately after power up. The memory contents is not corrupted as a further power cycle gives the correct results.

  I have noticed that the power up conditions are specified in the data sheet. There is no problem with tPU, as my first read is at least 100ms after Vdd is stable. However there may be a problem with tVR. I have measured the rise time from 0V to 2V as 95us/V.   My Vdd fall time is much slower than the spec, being 2.7ms/V.

Could you please explain the significance of these specifications. The memories are part of a complex design, and it would be difficult to change the Vdd rise and fall times without powering the memories from a special supply.

Is there a software solution to reset the memories after power up?

regards

Cosmo Little

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1 Solution
PradiptaB_11
Moderator
Moderator

Hi,

Please find the below KBA for more information on this topic.

Voltage Ramp Rate Required for F-RAM™ Devices - KBA204270

Re: FRAM power-up ramp rate specification

Your results indicate that the memory may be not able to configure itself properly as the data is not corrupted and the general reasoning for this is power supply issues.

Your settings seems to be fine. Can you please answer our below queries

1) How many devices are showing these behavior.

2) What are the steps you are following to test the memory devices ( testing procedure).

3) Can you provide the top marking for one of the device showing this behavior.

4) Can you share the schematics of the FRAM section with us

Thanks,

Pradipta.

View solution in original post

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3 Replies
PradiptaB_11
Moderator
Moderator

Hi,

Please find the below KBA for more information on this topic.

Voltage Ramp Rate Required for F-RAM™ Devices - KBA204270

Re: FRAM power-up ramp rate specification

Your results indicate that the memory may be not able to configure itself properly as the data is not corrupted and the general reasoning for this is power supply issues.

Your settings seems to be fine. Can you please answer our below queries

1) How many devices are showing these behavior.

2) What are the steps you are following to test the memory devices ( testing procedure).

3) Can you provide the top marking for one of the device showing this behavior.

4) Can you share the schematics of the FRAM section with us

Thanks,

Pradipta.

View solution in original post

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coli_4707641
New Contributor

Dear Pradipta,

    I see now that I interpreted the rise and fall time specs as maximums rather than minimums.  I am now confident that the possible problem is not power supply related.

     At the moment testing is slow, as I have to manually cycle the power to check that the memory read is correct. I will continue to test and will report back to you if I see any problems.

     The application is fitted with a power fail interrupt to give time to store data to the FRAMs before the power fails.

  Is there any advantage in placing the FRAMs in sleep mode before the power fails?  After the last write, the chip select goes high, so the memory should be write protected anyway.

     Attached part schematic for your information.(note 23LC1024 are replaced by CY15B104Q for non volatile memory option)

regards

Cosmo Little

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coli_4707641
New Contributor

Attachment

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