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Nor Flash
The NOR Flash Memory forum discusses critical safety features for automotive and industrial systems, and Semper NOR Flash Memory with ASIL-B compliant and ASIL-D-ready.
Hyper Flash
The HyperFlash NOR Flash memories Forum offers discussions on automotive advanced driver assistance systems (ADAS), automotive instrument cluster, automotive infotainment systems, and communication equipment.
Hyper RAM
HyperRAM™ memory Forum discusses self-refresh DRAM operating on the 12-pin HyperBus interface. With a read throughput up to 333 MB/s, the HyperRAM for SoCs with limited on-board RAM providing external scratch-pad memory for fast read and write operations.
Non Volatile RAM (F-RAM & NVSRAM)
Non-volatile RAM forum discusses Technology such as F-RAM and nvSRAM, which combine non-volatile data storage up to 16Mbit density with the high performance of RAM. These low-power memories offer high endurance, high data retention and instant non-volatility without external battery back-up, enabling system reliability and cost reduction.
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Hi,
I have designed a custom PCB with STM32H735 MCU and due to EoL and current unavailability of older HyperRAM S70KL1281 (that was originally used on ST-Micro's Discovery Kit) I decided to choose new HyperRAM S70KL1282. It's wired the same way as on discovery kit (including RWDS signal) and I was carefull about OSPI signal traces length matching.
I set up the MCU OSPI/HyperBus peripheral according to STM example and I use existing HyperRAM driver:
https://github.com/STMicroelectronics/stm32-s70kl1281
I fixed the initial latency from 6 to 7.
I can successfully read the device ID words and config reg 0,1.
The problem is that when I write some data at address 0 and read it back I found the data pattern writen with 8 bytes offset from the address 0 even I use always address 0 as argument to the R/W functions. I also tried enable memory mapped mode and access the RAM via pointer but I still got this strange offset. I also tried to lower the OSPI frequency by divider down to 33MHz but still any change. Contrary the users of old memory chip S70KL1281 doesn't report such problems. They shared the OSPI peripheral configuration that I tried to use so setting on MCU side (master) should be the same but I still have the 8B offset. I cannot get S70KL1281 to try. Any idea what's wrong? Do I need to set something in CR0/1 differently than POR values? Here are some of my code and debug terminal output to describe the issue:
{
uint8_t buff[64]={0};
int i;
buff[0]=0xab; buff[1]=0xcd; buff[2]=0xef; buff[3]=0xaa;
if (S70KL1281_Write(&XRAM, buff, 0, 16)!=S70KL1281_OK)
printf("Failed to write to HyperRAM\n");
for (i=0; i<32; i++)
printf("%02X ", buff[i]);
printf("\n");
if (S70KL1281_Read(&XRAM, buff, 0, 32)!=S70KL1281_OK)
printf("Failed to read from HyperRAM\n");
for (i=0; i<32; i++)
printf("%02X ", buff[i]);
printf("\n");
if (S70KL1281_Read(&XRAM, buff, 0, 32)!=S70KL1281_OK)
printf("Failed to read from HyperRAM\n");
for (i=0; i<32; i++)
printf("%02X ", buff[i]);
printf("\n");
}
The memory address is 0 but I get this:
Ext. OctoSPI HyperRAM ID: 0C81 0001
Manufacturer: Infineon, HyperRAM 2.0, rowbits: 13, colbits: 9
AB CD EF AA 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
57 47 57 5D D5 D7 8C 15 AB CD EF AA 00 00 00 00 00 00 00 00 00 00 00 00 D5 D5 57 5F D5 D5 5F 75
57 47 57 5D D5 D7 8C 15 AB CD EF AA 00 00 00 00 00 00 00 00 00 00 00 00 D5 D5 57 5F D5 D5 5F 75
There's some garbage in first 8 Bytes (57 47 57 5D D5 D7 CC 15 - uninitialized memory?) followed by correct pattern AB CD EF AA and trailing zeros from buffer
And the memory mapped mode:
{
__IO uint32_t *mem_addr = (__IO uint32_t *)(OCTOSPI2_BASE);
int i;
if (S70KL1281_EnableMemoryMappedMode(&XRAM)!=S70KL1281_OK)
printf("Failed to Enable Memory Mapped Mode\n");
else
printf("Memory Mapped Mode Enabled\n");
mem_addr[0]=0xABCDEFAA;
mem_addr[1]=0x12345678;
mem_addr[2]=0;
mem_addr[3]=0;
for (i=0; i<48; i++); // a shot delay, 46 read ok, 47 read garbage
printf("%08lX\n", mem_addr[0]);
printf("%08lX\n", mem_addr[0]);
printf("%08lX\n", mem_addr[0]); // 57 45 57 5D = "WEW]"
for (i=0; i<32/4; i++)
printf("%08lX ", mem_addr[i]);
printf("\n");
for (i=0; i<32; i++)
printf("%02X ", ((uint8_t *)mem_addr)[i]);
printf("\n");
}
Output is:
Ext. OctoSPI HyperRAM ID: 0C81 0001
Manufacturer: Infineon, HyperRAM 2.0, rowbits: 13, colbits: 9
Memory Mapped Mode Enabled
ABCDEFAA - this read changes according to for loop short delay, for shorter times it reads ABCDEFAA, for longer times it reads 5D574557
5D574557
5D574557
5D574557 158CD7D5 ABCDEFAA 12345678 00000000 00000000 5F57D5D5 755FF5D5
57 45 57 5D D5 D7 8C 15 AA EF CD AB 78 56 34 12 00 00 00 00 00 00 00 00 D5 D5 57 5F D5 F5 5F 75
Please let me know other users of this memory chip if it works for you properly or not and on what MCU/platform.
Hello,
I am currently developing software for CY15FRAMKIT-002 with a STM32F7 Nucleo Board. I was able to read the Device ID (RDID, command 9Fh) as 0000000006825150 in SPI mode and perform a write to and read from the memory successfully. Now, I configured the device to QPI mode with the following settings in the following sequence:
1. Set the Memory Latency to 0x2 by setting bits 7:4 in Configuration Register 1
2. Set the Register Latency to 0x2 by setting bits 7:6 in Configuration Register 5
3. Enabled QPI mode by setting bit 6 in Configuration Register 2
Once in QPI mode, I tried reading the Device ID (RDID, command 9Fh) but always got the response as 8888888888888888. When I tried to read and write the memory in QPI mode, that seems to work successfully. Then why does the Device ID command not repond with the correct value when it is a supported command in QPI mode? Is this an issue with the GPIO state for IO3 pin or something else? For information, my GPIO pin states are set as below for the STM32:
nCS: NOPULL
SCK: NOPULL
IO0: NOPULL
IO1: NOPULL
IO2: NOPULL
IO3: NOPULL
If this is a GPIO pin state issue, I would wonder why my read and writes work in QPI mode with the set latency.
Regards,
Surabhi
Hi,
I don't understand what is the difference between single chip enable and dual chip enable as option.
Could you explain simply how to access to memory and the advantage/ disadvantage for each single/dual chip enable ?
Best regards,
Show Less
Hello
We are using FRAM CY15B104QI memory in our project. We are using MSP430FR5994 microcontroller and we want to communicate with FRAM using SPI.
We have an issue with accessing the memory. We tried to read status register but we did not get expected values on MISO pin (MISO pin did not change its state at all). We made it work once but after that the same code did not work and we do not know what can be the issue.
I attached the archived image of workig example (the only one when we get the expected response). I also attached 2 screenshots of the signals on CS, CLK and MOSI that we measured using an osciloscope.
Are there any known issues with the memory or has this occurred to someone else?
Best regards
Show LessS29GL128P11TFI020 is discontinued (PDN PD_075_24 - see attached, page 6) and the replacement recommended on the same PDN is S29GL128S90TFI020. However, S29GL128P11TFI020 can work in either byte or word mode, and I don't see that capability with the recommended replacement part S29GL128S90TFI020. Of course, my legacy design uses the byte mode of operation. How can Infineon recommend a non 100% compatible replacement!? Can anyone confirm this, or am I missing something? Perhaps it is because this was originally a Cypress part.
Show LessHi,
I need the IBIS model for the below IC for SI analysis.
S25FL256SAGNFI001
Thanks
Bhavith
I want to read ID of Flash (S26KS128SDPBHB020)
2 My question is ,what is the "SA" meaning in the chart 7.1(The doc url: S26KS128SDPBHB020 Datasheet )
Which explain of "SA" is right ?
Thanks
Show Less
Hello,
I am having trouble getting read responses from a 4Mb fram. I have tried utilizing two different TI launchpads (C2000/Tiva) to communicate with the device. I have been running the clk speed in the 1Mhz to 2Mhz range. Also, I am utilizing a GPIO pin as a chip select as the spi CS peripheral de-asserts after each byte is transmitted. Pseudo code is as follows in my testing program:
set "CS" line high.
setup spi periph for Mode 0
// software reset.
write(0x66)
write(0x99)
delay for 300us
write(0x06)
write(0x02, 0x01, 0x12, 0x34, 0xaa, 0x55)
read(0x03, 0x01, 0x12, 0x34, 0x00, 0x00)
end program.
The parenthesis open indicates CS going low, and parenthesis closed indicates CS going high. In the program, my receive bytes are 0xFF, 0xFF. In other testing programs, I have tried writing to the status/config registers and I am getting 0xFF bytes as well.
I am including scope shots from the TI C2000 based board. Are there any steps that I am missing in getting the device to function? Thanks for the help.
Show Less