Static Timing Analysis

Project : BLE CapSense
Build Time : 09/03/15 15:27:46
Device : CY8C4247LQI-BL483
Temperature : -40C - 85C
VDDA : 3.30
VDDA_CTB : 3.30
VDDD : 3.30
VDDIO : 3.30
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 3.3
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CapSense_SampleClk(FFB) CapSense_SampleClk(FFB) 188.235 kHz 188.235 kHz N/A
CapSense_SenseClk(FFB) CapSense_SenseClk(FFB) 188.235 kHz 188.235 kHz N/A
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz N/A
CapSense_SampleClk CyHFCLK 188.235 kHz 188.235 kHz N/A
CapSense_SenseClk CyHFCLK 188.235 kHz 188.235 kHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A