Static Timing Analysis

Project : Design01
Build Time : 03/08/17 10:44:23
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 96.339 MHz
Clock_1 CyMASTER_CLK 100.000 kHz 100.000 kHz 32.215 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 10000ns(100 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\I2C:bI2C_UDB:clkgen_tc1_reg\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 32.215 MHz 31.041 9968.959
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,5) 1 \I2C:bI2C_UDB:clkgen_tc1_reg\ \I2C:bI2C_UDB:clkgen_tc1_reg\/clock_0 \I2C:bI2C_UDB:clkgen_tc1_reg\/q 1.250
Route 1 \I2C:bI2C_UDB:clkgen_tc1_reg\ \I2C:bI2C_UDB:clkgen_tc1_reg\/q \I2C:bI2C_UDB:cnt_reset\/main_7 8.666
macrocell4 U(0,4) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_7 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 4.014
macrocell8 U(1,5) 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 4.401
datapathcell1 U(0,2) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2C:bI2C_UDB:m_state_3\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 34.292 MHz 29.161 9970.839
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,2) 1 \I2C:bI2C_UDB:m_state_3\ \I2C:bI2C_UDB:m_state_3\/clock_0 \I2C:bI2C_UDB:m_state_3\/q 1.250
Route 1 \I2C:bI2C_UDB:m_state_3\ \I2C:bI2C_UDB:m_state_3\/q \I2C:bI2C_UDB:cnt_reset\/main_1 6.786
macrocell4 U(0,4) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_1 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 4.014
macrocell8 U(1,5) 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 4.401
datapathcell1 U(0,2) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2C:bI2C_UDB:m_state_1\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 34.965 MHz 28.600 9971.400
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,3) 1 \I2C:bI2C_UDB:m_state_1\ \I2C:bI2C_UDB:m_state_1\/clock_0 \I2C:bI2C_UDB:m_state_1\/q 1.250
Route 1 \I2C:bI2C_UDB:m_state_1\ \I2C:bI2C_UDB:m_state_1\/q \I2C:bI2C_UDB:cnt_reset\/main_3 6.225
macrocell4 U(0,4) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_3 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 4.014
macrocell8 U(1,5) 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 4.401
datapathcell1 U(0,2) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2C:bI2C_UDB:m_state_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 36.373 MHz 27.493 9972.507
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,5) 1 \I2C:bI2C_UDB:m_state_0\ \I2C:bI2C_UDB:m_state_0\/clock_0 \I2C:bI2C_UDB:m_state_0\/q 1.250
Route 1 \I2C:bI2C_UDB:m_state_0\ \I2C:bI2C_UDB:m_state_0\/q \I2C:bI2C_UDB:cnt_reset\/main_4 5.118
macrocell4 U(0,4) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_4 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 4.014
macrocell8 U(1,5) 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 4.401
datapathcell1 U(0,2) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2C:bI2C_UDB:scl_in_reg\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 36.789 MHz 27.182 9972.818
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(0,5) 1 \I2C:bI2C_UDB:scl_in_reg\ \I2C:bI2C_UDB:scl_in_reg\/clock_0 \I2C:bI2C_UDB:scl_in_reg\/q 1.250
Route 1 \I2C:bI2C_UDB:scl_in_reg\ \I2C:bI2C_UDB:scl_in_reg\/q \I2C:bI2C_UDB:cnt_reset\/main_5 4.807
macrocell4 U(0,4) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_5 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 4.014
macrocell8 U(1,5) 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 4.401
datapathcell1 U(0,2) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2C:bI2C_UDB:m_state_2\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 37.004 MHz 27.024 9972.976
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,4) 1 \I2C:bI2C_UDB:m_state_2\ \I2C:bI2C_UDB:m_state_2\/clock_0 \I2C:bI2C_UDB:m_state_2\/q 1.250
Route 1 \I2C:bI2C_UDB:m_state_2\ \I2C:bI2C_UDB:m_state_2\/q \I2C:bI2C_UDB:cnt_reset\/main_2 4.649
macrocell4 U(0,4) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_2 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 4.014
macrocell8 U(1,5) 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 4.401
datapathcell1 U(0,2) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2C:bI2C_UDB:m_state_4\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 37.007 MHz 27.022 9972.978
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,3) 1 \I2C:bI2C_UDB:m_state_4\ \I2C:bI2C_UDB:m_state_4\/clock_0 \I2C:bI2C_UDB:m_state_4\/q 1.250
Route 1 \I2C:bI2C_UDB:m_state_4\ \I2C:bI2C_UDB:m_state_4\/q \I2C:bI2C_UDB:cnt_reset\/main_0 4.647
macrocell4 U(0,4) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_0 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 4.014
macrocell8 U(1,5) 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 4.401
datapathcell1 U(0,2) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2C:bI2C_UDB:clkgen_tc1_reg\/q \I2C:bI2C_UDB:Master:ClkGen:u0\/cs_addr_1 37.608 MHz 26.590 9973.410
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,5) 1 \I2C:bI2C_UDB:clkgen_tc1_reg\ \I2C:bI2C_UDB:clkgen_tc1_reg\/clock_0 \I2C:bI2C_UDB:clkgen_tc1_reg\/q 1.250
Route 1 \I2C:bI2C_UDB:clkgen_tc1_reg\ \I2C:bI2C_UDB:clkgen_tc1_reg\/q \I2C:bI2C_UDB:cnt_reset\/main_7 8.666
macrocell4 U(0,4) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_7 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_clkgen_1\/main_1 3.534
macrocell5 U(0,5) 1 \I2C:bI2C_UDB:cs_addr_clkgen_1\ \I2C:bI2C_UDB:cs_addr_clkgen_1\/main_1 \I2C:bI2C_UDB:cs_addr_clkgen_1\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_clkgen_1\ \I2C:bI2C_UDB:cs_addr_clkgen_1\/q \I2C:bI2C_UDB:Master:ClkGen:u0\/cs_addr_1 2.310
datapathcell2 U(0,5) 1 \I2C:bI2C_UDB:Master:ClkGen:u0\ SETUP 4.130
Clock Skew 0.000
\I2C:Net_643_3\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 37.631 MHz 26.574 9973.426
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(0,5) 1 \I2C:Net_643_3\ \I2C:Net_643_3\/clock_0 \I2C:Net_643_3\/q 1.250
Route 1 \I2C:Net_643_3\ \I2C:Net_643_3\/q \I2C:bI2C_UDB:cnt_reset\/main_8 4.199
macrocell4 U(0,4) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_8 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 4.014
macrocell8 U(1,5) 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 4.401
datapathcell1 U(0,2) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2C:bI2C_UDB:clkgen_tc1_reg\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_1 39.938 MHz 25.039 9974.961
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,5) 1 \I2C:bI2C_UDB:clkgen_tc1_reg\ \I2C:bI2C_UDB:clkgen_tc1_reg\/clock_0 \I2C:bI2C_UDB:clkgen_tc1_reg\/q 1.250
Route 1 \I2C:bI2C_UDB:clkgen_tc1_reg\ \I2C:bI2C_UDB:clkgen_tc1_reg\/q \I2C:bI2C_UDB:cs_addr_shifter_1\/main_6 11.792
macrocell7 U(0,2) 1 \I2C:bI2C_UDB:cs_addr_shifter_1\ \I2C:bI2C_UDB:cs_addr_shifter_1\/main_6 \I2C:bI2C_UDB:cs_addr_shifter_1\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_1\ \I2C:bI2C_UDB:cs_addr_shifter_1\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_1 2.637
datapathcell1 U(0,2) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
SDA_1(0)/fb \I2C:bI2C_UDB:status_1\/main_6 96.339 MHz 10.380 31.287
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[5] 1 SDA_1(0) SDA_1(0)/in_clock SDA_1(0)/fb 1.303
Route 1 \I2C:Net_1109_1\ SDA_1(0)/fb \I2C:bI2C_UDB:status_1\/main_6 5.567
macrocell18 U(0,4) 1 \I2C:bI2C_UDB:status_1\ SETUP 3.510
Clock Skew 0.000
SCL_1(0)/fb \I2C:bI2C_UDB:scl_in_reg\/main_0 100.050 MHz 9.995 31.672
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P12[4] 1 SCL_1(0) SCL_1(0)/in_clock SCL_1(0)/fb 1.828
Route 1 \I2C:Net_1109_0\ SCL_1(0)/fb \I2C:bI2C_UDB:scl_in_reg\/main_0 4.657
macrocell20 U(0,5) 1 \I2C:bI2C_UDB:scl_in_reg\ SETUP 3.510
Clock Skew 0.000
SCL_1(0)/fb \I2C:bI2C_UDB:clk_eq_reg\/main_0 100.050 MHz 9.995 31.672
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P12[4] 1 SCL_1(0) SCL_1(0)/in_clock SCL_1(0)/fb 1.828
Route 1 \I2C:Net_1109_0\ SCL_1(0)/fb \I2C:bI2C_UDB:clk_eq_reg\/main_0 4.657
macrocell30 U(0,5) 1 \I2C:bI2C_UDB:clk_eq_reg\ SETUP 3.510
Clock Skew 0.000
SDA_1(0)/fb \I2C:bI2C_UDB:sda_in_reg\/main_0 105.474 MHz 9.481 32.186
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[5] 1 SDA_1(0) SDA_1(0)/in_clock SDA_1(0)/fb 1.303
Route 1 \I2C:Net_1109_1\ SDA_1(0)/fb \I2C:bI2C_UDB:sda_in_reg\/main_0 4.668
macrocell10 U(1,5) 1 \I2C:bI2C_UDB:sda_in_reg\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_1 \I2C:bI2C_UDB:m_reset\/main_0 2.664
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,2) 1 \I2C:bI2C_UDB:SyncCtl:CtrlReg\ \I2C:bI2C_UDB:SyncCtl:CtrlReg\/clock \I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_1 0.360
Route 1 \I2C:bI2C_UDB:control_1\ \I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_1 \I2C:bI2C_UDB:m_reset\/main_0 2.304
macrocell33 U(1,2) 1 \I2C:bI2C_UDB:m_reset\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_2 \I2C:bI2C_UDB:m_state_3\/main_2 2.998
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,2) 1 \I2C:bI2C_UDB:SyncCtl:CtrlReg\ \I2C:bI2C_UDB:SyncCtl:CtrlReg\/clock \I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_2 0.360
Route 1 \I2C:bI2C_UDB:control_2\ \I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_2 \I2C:bI2C_UDB:m_state_3\/main_2 2.638
macrocell12 U(0,2) 1 \I2C:bI2C_UDB:m_state_3\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_6 \I2C:bI2C_UDB:m_state_3\/main_0 3.336
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,2) 1 \I2C:bI2C_UDB:SyncCtl:CtrlReg\ \I2C:bI2C_UDB:SyncCtl:CtrlReg\/clock \I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_6 0.360
Route 1 \I2C:bI2C_UDB:control_6\ \I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_6 \I2C:bI2C_UDB:m_state_3\/main_0 2.976
macrocell12 U(0,2) 1 \I2C:bI2C_UDB:m_state_3\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:scl_in_last2_reg\/q \I2C:bI2C_UDB:bus_busy_reg\/main_2 3.536
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,4) 1 \I2C:bI2C_UDB:scl_in_last2_reg\ \I2C:bI2C_UDB:scl_in_last2_reg\/clock_0 \I2C:bI2C_UDB:scl_in_last2_reg\/q 1.250
Route 1 \I2C:bI2C_UDB:scl_in_last2_reg\ \I2C:bI2C_UDB:scl_in_last2_reg\/q \I2C:bI2C_UDB:bus_busy_reg\/main_2 2.286
macrocell29 U(1,4) 1 \I2C:bI2C_UDB:bus_busy_reg\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:status_2\/q \I2C:bI2C_UDB:status_2\/main_0 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,5) 1 \I2C:bI2C_UDB:status_2\ \I2C:bI2C_UDB:status_2\/clock_0 \I2C:bI2C_UDB:status_2\/q 1.250
macrocell17 U(1,5) 1 \I2C:bI2C_UDB:status_2\ \I2C:bI2C_UDB:status_2\/q \I2C:bI2C_UDB:status_2\/main_0 2.297
macrocell17 U(1,5) 1 \I2C:bI2C_UDB:status_2\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:lost_arb_reg\/q \I2C:bI2C_UDB:lost_arb_reg\/main_2 3.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,4) 1 \I2C:bI2C_UDB:lost_arb_reg\ \I2C:bI2C_UDB:lost_arb_reg\/clock_0 \I2C:bI2C_UDB:lost_arb_reg\/q 1.250
macrocell26 U(0,4) 1 \I2C:bI2C_UDB:lost_arb_reg\ \I2C:bI2C_UDB:lost_arb_reg\/q \I2C:bI2C_UDB:lost_arb_reg\/main_2 2.299
macrocell26 U(0,4) 1 \I2C:bI2C_UDB:lost_arb_reg\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:status_0\/q \I2C:bI2C_UDB:status_0\/main_0 3.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,4) 1 \I2C:bI2C_UDB:status_0\ \I2C:bI2C_UDB:status_0\/clock_0 \I2C:bI2C_UDB:status_0\/q 1.250
macrocell19 U(0,4) 1 \I2C:bI2C_UDB:status_0\ \I2C:bI2C_UDB:status_0\/q \I2C:bI2C_UDB:status_0\/main_0 2.301
macrocell19 U(0,4) 1 \I2C:bI2C_UDB:status_0\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:bus_busy_reg\/q \I2C:bI2C_UDB:bus_busy_reg\/main_6 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(1,4) 1 \I2C:bI2C_UDB:bus_busy_reg\ \I2C:bI2C_UDB:bus_busy_reg\/clock_0 \I2C:bI2C_UDB:bus_busy_reg\/q 1.250
macrocell29 U(1,4) 1 \I2C:bI2C_UDB:bus_busy_reg\ \I2C:bI2C_UDB:bus_busy_reg\/q \I2C:bI2C_UDB:bus_busy_reg\/main_6 2.306
macrocell29 U(1,4) 1 \I2C:bI2C_UDB:bus_busy_reg\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:Shifter:u0\/so_comb \I2C:sda_x_wire\/main_2 3.722
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,2) 1 \I2C:bI2C_UDB:Shifter:u0\ \I2C:bI2C_UDB:Shifter:u0\/clock \I2C:bI2C_UDB:Shifter:u0\/so_comb 0.800
Route 1 \I2C:bI2C_UDB:shift_data_out\ \I2C:bI2C_UDB:Shifter:u0\/so_comb \I2C:sda_x_wire\/main_2 2.922
macrocell32 U(0,3) 1 \I2C:sda_x_wire\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:scl_in_last_reg\/q \I2C:bI2C_UDB:scl_in_last2_reg\/main_0 3.832
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,4) 1 \I2C:bI2C_UDB:scl_in_last_reg\ \I2C:bI2C_UDB:scl_in_last_reg\/clock_0 \I2C:bI2C_UDB:scl_in_last_reg\/q 1.250
Route 1 \I2C:bI2C_UDB:scl_in_last_reg\ \I2C:bI2C_UDB:scl_in_last_reg\/q \I2C:bI2C_UDB:scl_in_last2_reg\/main_0 2.582
macrocell22 U(1,4) 1 \I2C:bI2C_UDB:scl_in_last2_reg\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
SDA_1(0)/fb \I2C:bI2C_UDB:sda_in_reg\/main_0 5.971
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[5] 1 SDA_1(0) SDA_1(0)/in_clock SDA_1(0)/fb 1.303
Route 1 \I2C:Net_1109_1\ SDA_1(0)/fb \I2C:bI2C_UDB:sda_in_reg\/main_0 4.668
macrocell10 U(1,5) 1 \I2C:bI2C_UDB:sda_in_reg\ HOLD 0.000
Clock Skew 0.000
SCL_1(0)/fb \I2C:bI2C_UDB:scl_in_reg\/main_0 6.485
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P12[4] 1 SCL_1(0) SCL_1(0)/in_clock SCL_1(0)/fb 1.828
Route 1 \I2C:Net_1109_0\ SCL_1(0)/fb \I2C:bI2C_UDB:scl_in_reg\/main_0 4.657
macrocell20 U(0,5) 1 \I2C:bI2C_UDB:scl_in_reg\ HOLD 0.000
Clock Skew 0.000
SCL_1(0)/fb \I2C:bI2C_UDB:clk_eq_reg\/main_0 6.485
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P12[4] 1 SCL_1(0) SCL_1(0)/in_clock SCL_1(0)/fb 1.828
Route 1 \I2C:Net_1109_0\ SCL_1(0)/fb \I2C:bI2C_UDB:clk_eq_reg\/main_0 4.657
macrocell30 U(0,5) 1 \I2C:bI2C_UDB:clk_eq_reg\ HOLD 0.000
Clock Skew 0.000
SDA_1(0)/fb \I2C:bI2C_UDB:status_1\/main_6 6.870
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[5] 1 SDA_1(0) SDA_1(0)/in_clock SDA_1(0)/fb 1.303
Route 1 \I2C:Net_1109_1\ SDA_1(0)/fb \I2C:bI2C_UDB:status_1\/main_6 5.567
macrocell18 U(0,4) 1 \I2C:bI2C_UDB:status_1\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
\I2C:sda_x_wire\/q SDA_1(0)_PAD:out 24.987
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(0,3) 1 \I2C:sda_x_wire\ \I2C:sda_x_wire\/clock_0 \I2C:sda_x_wire\/q 1.250
Route 1 \I2C:sda_x_wire\ \I2C:sda_x_wire\/q SDA_1(0)/pin_input 7.699
iocell1 P12[5] 1 SDA_1(0) SDA_1(0)/pin_input SDA_1(0)/pad_out 16.038
Route 1 SDA_1(0)_PAD SDA_1(0)/pad_out SDA_1(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2C:Net_643_3\/q SCL_1(0)_PAD:out 24.876
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(0,5) 1 \I2C:Net_643_3\ \I2C:Net_643_3\/clock_0 \I2C:Net_643_3\/q 1.250
Route 1 \I2C:Net_643_3\ \I2C:Net_643_3\/q SCL_1(0)/pin_input 7.011
iocell2 P12[4] 1 SCL_1(0) SCL_1(0)/pin_input SCL_1(0)/pad_out 16.615
Route 1 SCL_1(0)_PAD SCL_1(0)/pad_out SCL_1(0)_PAD:out 0.000
Clock Clock path delay 0.000