Static Timing Analysis

Project : SPIM_Example01
Build Time : 10/05/16 16:02:57
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
VDDA : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VDDOPAMP : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 34.656 MHz
UART_1_IntClock CyMASTER_CLK 461.538 kHz 461.538 kHz 36.641 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:sRX:RxShifter:u0\/f0_bus_stat_comb DMA_RX/dmareq 34.656 MHz 28.855 12.812
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ \UART_1:BUART:sRX:RxShifter:u0\/busclk \UART_1:BUART:sRX:RxShifter:u0\/f0_bus_stat_comb 7.210
Route 1 \UART_1:BUART:rx_fifonotempty\ \UART_1:BUART:sRX:RxShifter:u0\/f0_bus_stat_comb \UART_1:BUART:rx_status_5\/main_0 2.939
macrocell10 U(3,2) 1 \UART_1:BUART:rx_status_5\ \UART_1:BUART:rx_status_5\/main_0 \UART_1:BUART:rx_status_5\/q 3.350
Route 1 \UART_1:BUART:rx_status_5\ \UART_1:BUART:rx_status_5\/q \UART_1:BUART:sRX:RxSts\/status_5 2.902
statusicell2 U(3,1) 1 \UART_1:BUART:sRX:RxSts\ \UART_1:BUART:sRX:RxSts\/status_5 \UART_1:BUART:sRX:RxSts\/interrupt 3.910
Route 1 Net_124 \UART_1:BUART:sRX:RxSts\/interrupt DMA_RX/dmareq 7.727
drqcell1 [DrqContainer=(0)][DrqId=(0)] 1 DMA_RX SETUP 0.817
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb DMA_TX/dmareq 38.137 MHz 26.221 15.446
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/busclk \UART_1:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb 7.210
Route 1 \UART_1:BUART:tx_fifo_notfull\ \UART_1:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb \UART_1:BUART:tx_status_2\/main_0 3.621
macrocell5 U(3,5) 1 \UART_1:BUART:tx_status_2\ \UART_1:BUART:tx_status_2\/main_0 \UART_1:BUART:tx_status_2\/q 3.350
Route 1 \UART_1:BUART:tx_status_2\ \UART_1:BUART:tx_status_2\/q \UART_1:BUART:sTX:TxSts\/status_2 2.311
statusicell1 U(3,5) 1 \UART_1:BUART:sTX:TxSts\ \UART_1:BUART:sTX:TxSts\/status_2 \UART_1:BUART:sTX:TxSts\/interrupt 3.910
Route 1 Net_125 \UART_1:BUART:sTX:TxSts\/interrupt DMA_TX/dmareq 4.996
drqcell2 [DrqContainer=(0)][DrqId=(1)] 1 DMA_TX SETUP 0.823
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb DMA_TX/dmareq 47.340 MHz 21.124 20.543
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/busclk \UART_1:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb 7.210
Route 1 \UART_1:BUART:tx_fifo_notfull\ \UART_1:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb \UART_1:BUART:sTX:TxSts\/status_3 4.185
statusicell1 U(3,5) 1 \UART_1:BUART:sTX:TxSts\ \UART_1:BUART:sTX:TxSts\/status_3 \UART_1:BUART:sTX:TxSts\/interrupt 3.910
Route 1 Net_125 \UART_1:BUART:sTX:TxSts\/interrupt DMA_TX/dmareq 4.996
drqcell2 [DrqContainer=(0)][DrqId=(1)] 1 DMA_TX SETUP 0.823
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:rx_markspace_pre\/main_8 36.641 MHz 27.292 14.375
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_markspace_pre_split\/main_6 7.852
macrocell12 U(2,1) 1 \UART_1:BUART:rx_markspace_pre_split\ \UART_1:BUART:rx_markspace_pre_split\/main_6 \UART_1:BUART:rx_markspace_pre_split\/q 3.350
Route 1 \UART_1:BUART:rx_markspace_pre_split\ \UART_1:BUART:rx_markspace_pre_split\/q \UART_1:BUART:rx_markspace_pre\/main_8 2.298
macrocell33 U(2,1) 1 \UART_1:BUART:rx_markspace_pre\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_6 38.444 MHz 26.012 15.655
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_state_2_split\/main_5 6.572
macrocell14 U(2,2) 1 \UART_1:BUART:rx_state_2_split\ \UART_1:BUART:rx_state_2_split\/main_5 \UART_1:BUART:rx_state_2_split\/q 3.350
Route 1 \UART_1:BUART:rx_state_2_split\ \UART_1:BUART:rx_state_2_split\/q \UART_1:BUART:rx_state_2\/main_6 2.298
macrocell24 U(2,2) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_7 38.466 MHz 25.997 15.670
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_state_2_split_1\/main_7 6.544
macrocell13 U(3,2) 1 \UART_1:BUART:rx_state_2_split_1\ \UART_1:BUART:rx_state_2_split_1\/main_7 \UART_1:BUART:rx_state_2_split_1\/q 3.350
Route 1 \UART_1:BUART:rx_state_2_split_1\ \UART_1:BUART:rx_state_2_split_1\/q \UART_1:BUART:rx_state_2\/main_7 2.311
macrocell24 U(2,2) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_3\/main_7 40.159 MHz 24.901 16.766
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_state_3_split\/main_8 5.474
macrocell30 U(3,3) 1 \UART_1:BUART:rx_state_3_split\ \UART_1:BUART:rx_state_3_split\/main_8 \UART_1:BUART:rx_state_3_split\/q 3.350
Route 1 \UART_1:BUART:rx_state_3_split\ \UART_1:BUART:rx_state_3_split\/q \UART_1:BUART:rx_state_3\/main_7 2.285
macrocell23 U(3,3) 1 \UART_1:BUART:rx_state_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_load_fifo\/main_11 42.292 MHz 23.645 18.022
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_load_fifo_split\/main_7 4.205
macrocell1 U(3,4) 1 \UART_1:BUART:rx_load_fifo_split\ \UART_1:BUART:rx_load_fifo_split\/main_7 \UART_1:BUART:rx_load_fifo_split\/q 3.350
Route 1 \UART_1:BUART:rx_load_fifo_split\ \UART_1:BUART:rx_load_fifo_split\/q \UART_1:BUART:rx_load_fifo\/main_11 2.298
macrocell22 U(3,4) 1 \UART_1:BUART:rx_load_fifo\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_address_detected\/main_8 46.200 MHz 21.645 20.022
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_address_detected\/main_8 7.853
macrocell34 U(3,1) 1 \UART_1:BUART:rx_address_detected\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_markspace_pre\/main_4 46.243 MHz 21.625 20.042
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_markspace_pre\/main_4 7.833
macrocell33 U(2,1) 1 \UART_1:BUART:rx_markspace_pre\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 47.742 MHz 20.946 20.721
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 5.454
datapathcell3 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_3 49.133 MHz 20.353 21.314
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_state_2\/main_3 6.561
macrocell24 U(2,2) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_load_fifo\/main_5 50.073 MHz 19.971 21.696
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_load_fifo\/main_5 6.179
macrocell22 U(3,4) 1 \UART_1:BUART:rx_load_fifo\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:rx_state_stop1_reg\/q DMA_RX/dmareq 44.918 MHz 22.263 19.404
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,2) 1 \UART_1:BUART:rx_state_stop1_reg\ \UART_1:BUART:rx_state_stop1_reg\/clock_0 \UART_1:BUART:rx_state_stop1_reg\/q 1.250
Route 1 \UART_1:BUART:rx_state_stop1_reg\ \UART_1:BUART:rx_state_stop1_reg\/q \UART_1:BUART:rx_status_5\/main_1 2.307
macrocell10 U(3,2) 1 \UART_1:BUART:rx_status_5\ \UART_1:BUART:rx_status_5\/main_1 \UART_1:BUART:rx_status_5\/q 3.350
Route 1 \UART_1:BUART:rx_status_5\ \UART_1:BUART:rx_status_5\/q \UART_1:BUART:sRX:RxSts\/status_5 2.902
statusicell2 U(3,1) 1 \UART_1:BUART:sRX:RxSts\ \UART_1:BUART:sRX:RxSts\/status_5 \UART_1:BUART:sRX:RxSts\/interrupt 3.910
Route 1 Net_124 \UART_1:BUART:sRX:RxSts\/interrupt DMA_RX/dmareq 7.727
drqcell1 [DrqContainer=(0)][DrqId=(0)] 1 DMA_RX SETUP 0.817
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb DMA_TX/dmareq 52.102 MHz 19.193 22.474
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_1 4.184
statusicell1 U(3,5) 1 \UART_1:BUART:sTX:TxSts\ \UART_1:BUART:sTX:TxSts\/status_1 \UART_1:BUART:sTX:TxSts\/interrupt 3.910
Route 1 Net_125 \UART_1:BUART:sTX:TxSts\/interrupt DMA_TX/dmareq 4.996
drqcell2 [DrqContainer=(0)][DrqId=(1)] 1 DMA_TX SETUP 0.823
Clock Skew 0.000
\UART_1:BUART:sRX:RxSts\/interrupt DMA_RX/dmareq 79.529 MHz 12.574 29.093
Type Location Fanout Instance/Net Source Dest Delay (ns)
statusicell2 U(3,1) 1 \UART_1:BUART:sRX:RxSts\ \UART_1:BUART:sRX:RxSts\/clock \UART_1:BUART:sRX:RxSts\/interrupt 4.030
Route 1 Net_124 \UART_1:BUART:sRX:RxSts\/interrupt DMA_RX/dmareq 7.727
drqcell1 [DrqContainer=(0)][DrqId=(0)] 1 DMA_RX SETUP 0.817
Clock Skew 0.000
\UART_1:BUART:sTX:TxSts\/interrupt DMA_TX/dmareq 101.533 MHz 9.849 31.818
Type Location Fanout Instance/Net Source Dest Delay (ns)
statusicell1 U(3,5) 1 \UART_1:BUART:sTX:TxSts\ \UART_1:BUART:sTX:TxSts\/clock \UART_1:BUART:sTX:TxSts\/interrupt 4.030
Route 1 Net_125 \UART_1:BUART:sTX:TxSts\/interrupt DMA_TX/dmareq 4.996
drqcell2 [DrqContainer=(0)][DrqId=(1)] 1 DMA_TX SETUP 0.823
Clock Skew 0.000
Path Delay Requirement : 2166.67ns(461.538 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_markspace_pre\/main_8 39.979 MHz 25.013 2141.654
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(2,4) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_postpoll\/main_0 3.403
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_markspace_pre_split\/main_6 7.852
macrocell12 U(2,1) 1 \UART_1:BUART:rx_markspace_pre_split\ \UART_1:BUART:rx_markspace_pre_split\/main_6 \UART_1:BUART:rx_markspace_pre_split\/q 3.350
Route 1 \UART_1:BUART:rx_markspace_pre_split\ \UART_1:BUART:rx_markspace_pre_split\/q \UART_1:BUART:rx_markspace_pre\/main_8 2.298
macrocell33 U(2,1) 1 \UART_1:BUART:rx_markspace_pre\ SETUP 3.510
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_markspace_pre\/main_8 39.990 MHz 25.006 2141.661
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(2,4) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
Route 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_postpoll\/main_2 3.396
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_2 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_markspace_pre_split\/main_6 7.852
macrocell12 U(2,1) 1 \UART_1:BUART:rx_markspace_pre_split\ \UART_1:BUART:rx_markspace_pre_split\/main_6 \UART_1:BUART:rx_markspace_pre_split\/q 3.350
Route 1 \UART_1:BUART:rx_markspace_pre_split\ \UART_1:BUART:rx_markspace_pre_split\/q \UART_1:BUART:rx_markspace_pre\/main_8 2.298
macrocell33 U(2,1) 1 \UART_1:BUART:rx_markspace_pre\ SETUP 3.510
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_state_2\/main_6 42.135 MHz 23.733 2142.934
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(2,4) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_postpoll\/main_0 3.403
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_state_2_split\/main_5 6.572
macrocell14 U(2,2) 1 \UART_1:BUART:rx_state_2_split\ \UART_1:BUART:rx_state_2_split\/main_5 \UART_1:BUART:rx_state_2_split\/q 3.350
Route 1 \UART_1:BUART:rx_state_2_split\ \UART_1:BUART:rx_state_2_split\/q \UART_1:BUART:rx_state_2\/main_6 2.298
macrocell24 U(2,2) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_state_2\/main_6 42.148 MHz 23.726 2142.941
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(2,4) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
Route 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_postpoll\/main_2 3.396
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_2 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_state_2_split\/main_5 6.572
macrocell14 U(2,2) 1 \UART_1:BUART:rx_state_2_split\ \UART_1:BUART:rx_state_2_split\/main_5 \UART_1:BUART:rx_state_2_split\/q 3.350
Route 1 \UART_1:BUART:rx_state_2_split\ \UART_1:BUART:rx_state_2_split\/q \UART_1:BUART:rx_state_2\/main_6 2.298
macrocell24 U(2,2) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_state_2\/main_7 42.162 MHz 23.718 2142.949
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(2,4) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_postpoll\/main_0 3.403
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_state_2_split_1\/main_7 6.544
macrocell13 U(3,2) 1 \UART_1:BUART:rx_state_2_split_1\ \UART_1:BUART:rx_state_2_split_1\/main_7 \UART_1:BUART:rx_state_2_split_1\/q 3.350
Route 1 \UART_1:BUART:rx_state_2_split_1\ \UART_1:BUART:rx_state_2_split_1\/q \UART_1:BUART:rx_state_2\/main_7 2.311
macrocell24 U(2,2) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_state_2\/main_7 42.175 MHz 23.711 2142.956
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(2,4) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
Route 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_postpoll\/main_2 3.396
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_2 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_state_2_split_1\/main_7 6.544
macrocell13 U(3,2) 1 \UART_1:BUART:rx_state_2_split_1\ \UART_1:BUART:rx_state_2_split_1\/main_7 \UART_1:BUART:rx_state_2_split_1\/q 3.350
Route 1 \UART_1:BUART:rx_state_2_split_1\ \UART_1:BUART:rx_state_2_split_1\/q \UART_1:BUART:rx_state_2\/main_7 2.311
macrocell24 U(2,2) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 42.856 MHz 23.334 2143.333
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(3,5) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 4.296
macrocell3 U(2,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.918
datapathcell2 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 42.915 MHz 23.302 2143.365
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(2,5) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 4.264
macrocell3 U(2,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.918
datapathcell2 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 43.085 MHz 23.210 2143.457
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:counter_load_not\/main_2 4.422
macrocell3 U(2,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.918
datapathcell2 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 43.446 MHz 23.017 2143.650
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(2,5) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 3.979
macrocell3 U(2,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.918
datapathcell2 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\UART_1:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb DMA_TX/dmareq 18.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/busclk \UART_1:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb 7.210
Route 1 \UART_1:BUART:tx_fifo_notfull\ \UART_1:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb \UART_1:BUART:sTX:TxSts\/status_3 4.185
statusicell1 U(3,5) 1 \UART_1:BUART:sTX:TxSts\ \UART_1:BUART:sTX:TxSts\/status_3 \UART_1:BUART:sTX:TxSts\/interrupt 2.460
Route 1 Net_125 \UART_1:BUART:sTX:TxSts\/interrupt DMA_TX/dmareq 4.996
drqcell2 [DrqContainer=(0)][DrqId=(1)] 1 DMA_TX HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb DMA_TX/dmareq 23.948
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/busclk \UART_1:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb 7.210
Route 1 \UART_1:BUART:tx_fifo_notfull\ \UART_1:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb \UART_1:BUART:tx_status_2\/main_0 3.621
macrocell5 U(3,5) 1 \UART_1:BUART:tx_status_2\ \UART_1:BUART:tx_status_2\/main_0 \UART_1:BUART:tx_status_2\/q 3.350
Route 1 \UART_1:BUART:tx_status_2\ \UART_1:BUART:tx_status_2\/q \UART_1:BUART:sTX:TxSts\/status_2 2.311
statusicell1 U(3,5) 1 \UART_1:BUART:sTX:TxSts\ \UART_1:BUART:sTX:TxSts\/status_2 \UART_1:BUART:sTX:TxSts\/interrupt 2.460
Route 1 Net_125 \UART_1:BUART:sTX:TxSts\/interrupt DMA_TX/dmareq 4.996
drqcell2 [DrqContainer=(0)][DrqId=(1)] 1 DMA_TX HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxShifter:u0\/f0_bus_stat_comb DMA_RX/dmareq 26.588
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ \UART_1:BUART:sRX:RxShifter:u0\/busclk \UART_1:BUART:sRX:RxShifter:u0\/f0_bus_stat_comb 7.210
Route 1 \UART_1:BUART:rx_fifonotempty\ \UART_1:BUART:sRX:RxShifter:u0\/f0_bus_stat_comb \UART_1:BUART:rx_status_5\/main_0 2.939
macrocell10 U(3,2) 1 \UART_1:BUART:rx_status_5\ \UART_1:BUART:rx_status_5\/main_0 \UART_1:BUART:rx_status_5\/q 3.350
Route 1 \UART_1:BUART:rx_status_5\ \UART_1:BUART:rx_status_5\/q \UART_1:BUART:sRX:RxSts\/status_5 2.902
statusicell2 U(3,1) 1 \UART_1:BUART:sRX:RxSts\ \UART_1:BUART:sRX:RxSts\/status_5 \UART_1:BUART:sRX:RxSts\/interrupt 2.460
Route 1 Net_124 \UART_1:BUART:sRX:RxSts\/interrupt DMA_RX/dmareq 7.727
drqcell1 [DrqContainer=(0)][DrqId=(0)] 1 DMA_RX HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.132
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 5.031
macrocell27 U(2,4) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.132
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 5.031
macrocell28 U(2,4) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 6.132
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.031
macrocell35 U(2,4) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_6 13.450
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_state_2_split\/main_10 6.701
macrocell14 U(2,2) 1 \UART_1:BUART:rx_state_2_split\ \UART_1:BUART:rx_state_2_split\/main_10 \UART_1:BUART:rx_state_2_split\/q 3.350
Route 1 \UART_1:BUART:rx_state_2_split\ \UART_1:BUART:rx_state_2_split\/q \UART_1:BUART:rx_state_2\/main_6 2.298
macrocell24 U(2,2) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 15.736
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 5.454
datapathcell3 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_3 15.744
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_state_0\/main_3 5.462
macrocell21 U(2,3) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_load_fifo\/main_5 16.461
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_load_fifo\/main_5 6.179
macrocell22 U(3,4) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_3 16.461
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_status_3\/main_3 6.179
macrocell31 U(3,4) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_3 16.843
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_state_2\/main_3 6.561
macrocell24 U(2,2) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_markspace_pre\/main_4 18.115
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.101
Route 1 Net_106 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.831
macrocell7 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_markspace_pre\/main_4 7.833
macrocell33 U(2,1) 1 \UART_1:BUART:rx_markspace_pre\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:sTX:TxSts\/interrupt DMA_TX/dmareq 9.026
Type Location Fanout Instance/Net Source Dest Delay (ns)
statusicell1 U(3,5) 1 \UART_1:BUART:sTX:TxSts\ \UART_1:BUART:sTX:TxSts\/clock \UART_1:BUART:sTX:TxSts\/interrupt 4.030
Route 1 Net_125 \UART_1:BUART:sTX:TxSts\/interrupt DMA_TX/dmareq 4.996
drqcell2 [DrqContainer=(0)][DrqId=(1)] 1 DMA_TX HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxSts\/interrupt DMA_RX/dmareq 11.757
Type Location Fanout Instance/Net Source Dest Delay (ns)
statusicell2 U(3,1) 1 \UART_1:BUART:sRX:RxSts\ \UART_1:BUART:sRX:RxSts\/clock \UART_1:BUART:sRX:RxSts\/interrupt 4.030
Route 1 Net_124 \UART_1:BUART:sRX:RxSts\/interrupt DMA_RX/dmareq 7.727
drqcell1 [DrqContainer=(0)][DrqId=(0)] 1 DMA_RX HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb DMA_TX/dmareq 16.920
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_1 4.184
statusicell1 U(3,5) 1 \UART_1:BUART:sTX:TxSts\ \UART_1:BUART:sTX:TxSts\/status_1 \UART_1:BUART:sTX:TxSts\/interrupt 2.460
Route 1 Net_125 \UART_1:BUART:sTX:TxSts\/interrupt DMA_TX/dmareq 4.996
drqcell2 [DrqContainer=(0)][DrqId=(1)] 1 DMA_TX HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_state_stop1_reg\/q DMA_RX/dmareq 19.996
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,2) 1 \UART_1:BUART:rx_state_stop1_reg\ \UART_1:BUART:rx_state_stop1_reg\/clock_0 \UART_1:BUART:rx_state_stop1_reg\/q 1.250
Route 1 \UART_1:BUART:rx_state_stop1_reg\ \UART_1:BUART:rx_state_stop1_reg\/q \UART_1:BUART:rx_status_5\/main_1 2.307
macrocell10 U(3,2) 1 \UART_1:BUART:rx_status_5\ \UART_1:BUART:rx_status_5\/main_1 \UART_1:BUART:rx_status_5\/q 3.350
Route 1 \UART_1:BUART:rx_status_5\ \UART_1:BUART:rx_status_5\/q \UART_1:BUART:sRX:RxSts\/status_5 2.902
statusicell2 U(3,1) 1 \UART_1:BUART:sRX:RxSts\ \UART_1:BUART:sRX:RxSts\/status_5 \UART_1:BUART:sRX:RxSts\/interrupt 2.460
Route 1 Net_124 \UART_1:BUART:sRX:RxSts\/interrupt DMA_RX/dmareq 7.727
drqcell1 [DrqContainer=(0)][DrqId=(0)] 1 DMA_RX HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_address_detected\/q \UART_1:BUART:rx_address_detected\/main_11 3.553
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(3,1) 1 \UART_1:BUART:rx_address_detected\ \UART_1:BUART:rx_address_detected\/clock_0 \UART_1:BUART:rx_address_detected\/q 1.250
macrocell34 U(3,1) 1 \UART_1:BUART:rx_address_detected\ \UART_1:BUART:rx_address_detected\/q \UART_1:BUART:rx_address_detected\/main_11 2.303
macrocell34 U(3,1) 1 \UART_1:BUART:rx_address_detected\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_load_fifo\/main_1 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(2,4) 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/clock_0 \UART_1:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_load_fifo\/main_1 2.306
macrocell22 U(3,4) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_status_3\/main_0 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(2,4) 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/clock_0 \UART_1:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_status_3\/main_0 2.306
macrocell31 U(3,4) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 3.592
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 2.592
macrocell15 U(2,5) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 3.601
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 2.601
macrocell16 U(2,5) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 3.601
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 2.601
macrocell18 U(2,5) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_markspace_pre\/q \UART_1:BUART:rx_markspace_status\/main_8 3.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(2,1) 1 \UART_1:BUART:rx_markspace_pre\ \UART_1:BUART:rx_markspace_pre\/clock_0 \UART_1:BUART:rx_markspace_pre\/q 1.250
Route 1 \UART_1:BUART:rx_markspace_pre\ \UART_1:BUART:rx_markspace_pre\/q \UART_1:BUART:rx_markspace_status\/main_8 2.601
macrocell29 U(2,1) 1 \UART_1:BUART:rx_markspace_status\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_markspace_pre\/q \UART_1:BUART:rx_markspace_pre\/main_7 3.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(2,1) 1 \UART_1:BUART:rx_markspace_pre\ \UART_1:BUART:rx_markspace_pre\/clock_0 \UART_1:BUART:rx_markspace_pre\/q 1.250
macrocell33 U(2,1) 1 \UART_1:BUART:rx_markspace_pre\ \UART_1:BUART:rx_markspace_pre\/q \UART_1:BUART:rx_markspace_pre\/main_7 2.601
macrocell33 U(2,1) 1 \UART_1:BUART:rx_markspace_pre\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:pollcount_1\/main_2 3.878
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(2,4) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
macrocell27 U(2,4) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:pollcount_1\/main_2 2.628
macrocell27 U(2,4) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_1\/main_4 3.882
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(2,4) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
Route 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_1\/main_4 2.632
macrocell27 U(2,4) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 30.281
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,5) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_101/main_0 4.191
macrocell2 U(3,5) 1 Net_101 Net_101/main_0 Net_101/q 3.350
Route 1 Net_101 Net_101/q Tx_1(0)/pin_input 5.733
iocell9 P0[1] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 15.757
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000