1 Reply Latest reply on Jul 18, 2017 1:50 AM by bhwj

    Warning: sta.M0019: MainBoard_timing.html: Warning-1366: Setup time violation found in a path from clock ( CyHFCLK ) to clock (

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      UDB Timer connected to HFCLK directly, an external CLK (TCXO 32MHz) used.

         

      When compile it always get this warning.

         

      Warning: sta.M0019: MainBoard_timing.html: Warning-1366: Setup time violation found in a path from clock ( CyHFCLK ) to clock .

         

      And here is the attached html generated by the compiler.

         

       

         

      So my question is :

         

      #1. what is the problem of this? it said setup time, I am not quite understand this.

         

      #2. As the timer is sensitive to the accuracy and precision, so any performance impact?