Could you attach your project so that we can have a look into it?
OK, how can I send you the project confidentially. I don't want to put our source code up on the web for anyone to see.
I'm also attaching an image showing what happens when we drive a triangle signal into bufin. The two waves you see are the analog value of bufout and the ADC readings, both during sampling.
Since you are limited to VDD/2, I would suggest double checking the settings; The VDD/2 is a limit for one of the SAR ADC settings for range measurement limits. Also, from your graph of the data, it looks pretty accurate besides a difference of small constant offsets; I would attribute the x-delay to sample-time-delay, but not sure about the peaks being different amplitude. Possibly there is some resistance/parasitic components on your ADC readings.
OK, we solved the problem, but don't know why it works. The solution was:
1. Switch one of our opamps from OA1 to the previously-unused OA2. This seemed to make the switching fabric choose a less complex path for our signal
2. Reassigned a pin on our FRAM component (FHOLD, which doesn't actually connect to the chip) from p3.3 to p1.0.
Only by doing both of these things does the problem clean up.
The settings were quite clear -- we were set for a 0-2.048v range, and parasitics are pretty minimal. This seems to have been an issue of the switching fabric somehow mixing our signal with something, draining it to somewhere, or ?
A bit scary and very confounding.