3 Replies Latest reply on Sep 12, 2017 3:00 PM by user_342122993

    Calculating Max Number of possible ISRs per second


      I want to calculate how many ISRs a psoc 5lp with a 40Mhz master/bus clock can handle. The psoc5 has a cortex m3 so each ISR should trigger 12 clock cycles after the interrupt controller receives the interrupt request, furthermore, the delay till the execution of the next ISR can be as less as 6 clock cycles thanks to tail-chaining. Assuming the code in my ISR only takes 2 cycles then does that mean that I can have a theoretical maximum of (40*10^6)/20 = 2,000,000 interrupts per second ?!


      I want to use a psoc to drive 3 stepper motors (with a stepper driver) so basically I set a counter to the number of steps I want the stepper to take and connect the output of a pwm to the count input through a not gate so that I count the falling edge of each pulse. The Counter generates an interrupt that stops the pwm once it reaches its terminal count. I intend to use ISRs to decrement the period of the pwm component so that I can apply an acceleration profile to the stepper. I can create a custom UDB component to do the same in hardware provided my acceleration profile is trapezoidal however I wanted to know if its possible to get similar results using interrupts.


      I dont need the code in main to run while the ISRs are being executed since until the stepper completes the desired number of steps the code in main wont need to do anything.

        • 1. Re: Calculating Max Number of possible ISRs per second

          Your ISR handler code will be more than 2 cycles: The CPU needs to push some registers (6) to stack, execute your code, execute thr return instruction which pops off the registers again.


          My experiences were: 2000 interrupts per second with a reasonable handler on a PSoC4 runs smoothly.


          Let us look at your problem from another point of view: Steppers run with 100 to 1000 steps per second. When you want to increase the PWM frequency after every step you will be with two motors (even with tree) on the right side. Lean back ;-)


          On a PSoC 5 you may think about to develop a UDB-based component using Verilog hardware definition language. This component should do  the speed ramp calculation and limiting all by itself. Complicated job, but it will in the end run without any CPU intervention, just setup, fire and wait until done.





          • 2. Re: Calculating Max Number of possible ISRs per second

            Thanks. I've been working on a Verilog implementation for a trapezoidal ramp. I'm using micro-stepping and the minimum pulse width the stepper driver works with is 1us so I figured that a 500KHz pulse train is comfortable thus the need to ramp up to it- I have an appropriate gearbox ahead of the stepper so losing torque with speed isn't an issue.


            I was just really curious to know what refresh rate I could get with ISRs alone as the cortex-M3 is well suited for back to back ISR execution and since the arduino can handle 4000 interrupts a second I figured that a cortex-m3 at more than twice the clock speed would have a much higher tolerance but I don't how much. Think I'll just use the systick timer to figure out how many cycles my ISR takes.

            • 3. Re: Calculating Max Number of possible ISRs per second

              To check how many CPU clocks spent to rise ISR and time inside ISR you can use StopWatch custom component, which can be found in this thread:

              How to perform unit testing for developed c code in Creator ?

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