8 Replies Latest reply on Mar 31, 2020 7:21 PM by DrMo_1392206

    Calculating Max Number of possible ISRs per second

      I want to calculate how many ISRs a psoc 5lp with a 40Mhz master/bus clock can handle. The psoc5 has a cortex m3 so each ISR should trigger 12 clock cycles after the interrupt controller receives the interrupt request, furthermore, the delay till the execution of the next ISR can be as less as 6 clock cycles thanks to tail-chaining. Assuming the code in my ISR only takes 2 cycles then does that mean that I can have a theoretical maximum of (40*10^6)/20 = 2,000,000 interrupts per second ?!

         

      I want to use a psoc to drive 3 stepper motors (with a stepper driver) so basically I set a counter to the number of steps I want the stepper to take and connect the output of a pwm to the count input through a not gate so that I count the falling edge of each pulse. The Counter generates an interrupt that stops the pwm once it reaches its terminal count. I intend to use ISRs to decrement the period of the pwm component so that I can apply an acceleration profile to the stepper. I can create a custom UDB component to do the same in hardware provided my acceleration profile is trapezoidal however I wanted to know if its possible to get similar results using interrupts.

         

      I dont need the code in main to run while the ISRs are being executed since until the stepper completes the desired number of steps the code in main wont need to do anything.

        • 1. Re: Calculating Max Number of possible ISRs per second
          JoMe_264151

          Your ISR handler code will be more than 2 cycles: The CPU needs to push some registers (6) to stack, execute your code, execute thr return instruction which pops off the registers again.

             

          My experiences were: 2000 interrupts per second with a reasonable handler on a PSoC4 runs smoothly.

             

          Let us look at your problem from another point of view: Steppers run with 100 to 1000 steps per second. When you want to increase the PWM frequency after every step you will be with two motors (even with tree) on the right side. Lean back ;-)

             

          On a PSoC 5 you may think about to develop a UDB-based component using Verilog hardware definition language. This component should do  the speed ramp calculation and limiting all by itself. Complicated job, but it will in the end run without any CPU intervention, just setup, fire and wait until done.

             

           

             

          Bob

          • 2. Re: Calculating Max Number of possible ISRs per second

            Thanks. I've been working on a Verilog implementation for a trapezoidal ramp. I'm using micro-stepping and the minimum pulse width the stepper driver works with is 1us so I figured that a 500KHz pulse train is comfortable thus the need to ramp up to it- I have an appropriate gearbox ahead of the stepper so losing torque with speed isn't an issue.

               

            I was just really curious to know what refresh rate I could get with ISRs alone as the cortex-M3 is well suited for back to back ISR execution and since the arduino can handle 4000 interrupts a second I figured that a cortex-m3 at more than twice the clock speed would have a much higher tolerance but I don't how much. Think I'll just use the systick timer to figure out how many cycles my ISR takes.

            • 3. Re: Calculating Max Number of possible ISRs per second
              BoTa_264741

              To check how many CPU clocks spent to rise ISR and time inside ISR you can use StopWatch custom component, which can be found in this thread:

              How to perform unit testing for developed c code in Creator ?

              1 of 1 people found this helpful
              • 4. Re: Calculating Max Number of possible ISRs per second
                DrMo_1392206

                Still loving the PSoc5 LP!

                I'm running an interrupt at 200000 per second. Yes, 200 KHz!.

                System clock of 78MHz

                There isn't much time to do anything else but my ISR.. so I plan to move some stuff out into hardware, maybe some DMA, etc.

                2KHz is pretty leisurely in my book. This chip can do better than that for sure. I wager that 500KHz is possible, but perhaps that's pushing it..

                I'm even am able to communicate over USB with the small amount of time I have left (although USB does seem to mess with my ISR timing)

                 

                To see how much time my ISR spent, I just added an extra bit to a command register, brought it to a pin, set it high at entry and low at exit, and slapped a scope on it.

                4 microseconds high (in the body of the ISR) and 1 microsecond low.

                I'm reading 2 ADC, writing 2 DAC, doing some signal processing with integer multiplies, shifts, compares, etc.

                150 lines of code in the ISR.

                 

                If you have a 'scope, this approach might be easier than a custom component.

                (the custom component will let you do a bit more, though.)

                 

                Dr. Drew

                • 5. Re: Calculating Max Number of possible ISRs per second
                  BoTa_264741

                  Dr. Drew,

                  May I ask what kind of control you implementing with ADC and DAC?

                  /odissey1

                  • 6. Re: Calculating Max Number of possible ISRs per second
                    DrMo_1392206

                    It's a sensing application. I send out a stimulus, evaluate the response, and determine if something is present or not.

                    You have a control application at this bandwidth in mind? I do a little of that too. If it's on a different thread, point me to it. :-)

                    • 7. Re: Calculating Max Number of possible ISRs per second
                      BoTa_264741

                      Dr. Drew,

                      I was thinking this is for galvo / voice coil control.

                      /odissey1

                      • 8. Re: Calculating Max Number of possible ISRs per second
                        DrMo_1392206

                        Definitely getting off topic, Odissey.. but I'd test that by running a low frequency square wave (current? voltage?) into the galvo and seeing how whatever you are using for feedback(?) responds. Triangle wave? Try a lower test frequency. Exponential decay? Any resonance? what's the rough time constant? "How quickly does it react to the sudden change in input?" Try to see the delay from that change in drive to change in feedback.. An ISR that has at least a few chances to run in that decay time constant (or half cycle of resonance) would be minimally good enough.. you may want to go a lot faster, though, depending on how tight you want the control to be.. how "nice" the response is. You can only typically push a system "so far" past what it does open loop. too much drive, too much heat, etc.. If you can measure a definite "no significant response" time, that's an upper limit. Poles can be moved. Zeros, not so much.

                         

                        The Delta Sigma converter would be my choice for feedback for a single galvo. You can run it at low bit res and high rate for lower delay.. but also keep a running average (use the DelSig as a sense input to a Kalman filter) to increase the sensing resolution. The Delta Sigma, (one available on these things), is amazing.. all the bits you want, practically.. run it nonstop to milk the data from it. ;-) Often we want high positioning resolution from a galvo application.

                         

                        Dr. Drew