5 Replies Latest reply on Aug 4, 2017 3:04 AM by user_1377889

    Timer Clarification

    sunil.prasad

      Hello everyone,

         

      I'm using PSoC 5LP(CY8C586LTI-LP038) with PSoC Creator version 3.3.

         

      Iam trying to capture the PWM from Futaba R617FS. As of now only one channel is connected as input to the PSoC.

         

      The timer with period 16.043 ms is used. Trigger mode is Rising edge, capture mode is Falling edge,interrupt is enabled only on the Terminal Count. ISR will Send Character 'A' , whenever it is raised.

         

      Pin_2 is been used to monitor the output.

         

      The questions are:

         

      1. In the attached project "Timer_1"  configuration, how the Reset functionality works? I have followed the explanation provided in data sheet but not able to find the solution.

         

      2. Irrespective of the Channel 1 input Terminal count interrupt should be raised or not ?

         

      3. The APIs  as given in the attached project Timer_1_STATUS, and Timer_1_EnableTrigger(), how are they functioning in the attached project?

         

      please provide explanations for the same.

         

      Thank you in advance. 

        • 1. Re: Timer Clarification
          user_242978793

          Add a Sync component to insure trigger is correct.

          • 2. Re: Timer Clarification
            user_242978793

            Also update your Psoc Creator to Psoc Creator 4.0 SP 1. I am sending you an example for you to study there is a PDF file to explain it.

            • 3. Re: Timer Clarification
              user_1377889

              Keep in mind that the "reset" function of a timer component is asynchronous. So the signal has to stay for a low to high transition of the clock to reset. Solutions are

                 

              Using a Pulse Converter component (Digital -> Utilities)

                 

              Using software to stop, reload and restart the timer.

                 

              Last, but not least: Current version of Creator is 4.1 (not 4.0)

                 

               

                 

              Bob

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              • 4. Re: Timer Clarification
                sunil.prasad

                Thank you Bob Marlowe and bobgoar for response.

                   

                I checked the project you uploaded and it clarified many doubts. I read the datasheet too. In most of the example projects provided in PSoC creator, the reset is given a Logic low. So how  the timer is getting reloaded? Is Timer resets on its own? Can you please provide some more explanation about the reset. It would be helpful for me.

                   

                Thank you in Advance.

                • 5. Re: Timer Clarification
                  user_1377889

                  Resetting the Timer Component does a bit (or byte?) more than just reloading the counter. The reload is done at tc automatically. On some (different) timer components you may specify explicitly when a reload should be performed.

                     

                  My best experiences for measuring times are done with a Counter Component. This has got a capture feature which saves the current value, gives me an interrupt and allows for reading of the captured value while the counter still runs. An enable input allows for counting only the high-phase of the incoming signal. Count input is an internal clock. When high precision is needed this clock should be crystal-based.

                     

                   

                     

                  Bob

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