I just modeled the circuit only in CC3.0sp2, it worked. I took the same circuit into 4.0 and it appears to be working there also,.
I suspect that it gets to be a problem when the UDB is almost full. I can live with it in this case.
wsm, Having bus clock violation at less than 24MHz means that design is really overloaded. The UDB saturation at -80% indicates that almost all "unique P-terms" are used (it will never reach 100%), which means that there is a routing problem (not enough internal connections to route signals). In this situation fitter is trying to optimize the internal web of connections, it does not works well, and max. allowed bus frequency drops down. I observed that in such situations adding a pin may suddenly dramatically change entire routing and thus timing and signal integrity. So my thinking that optimizing (shrinking) design should alleviate the problem. Reducing bus clock works same direction. Both Counter interrupts will fire simultaneously. One isr should suffice. What matters is Counter settings and code inside isr resetting the Counter.
Interesting. I was thinking along the same lines, dropping a couple of counters for not-yet used channels. I had not thought about dropping all of the individual isr's. That is a good idea, I can make it work.
Is there any documentation on determining when the design is saturated?
I had tried using a mux and a single counter, but I had trouble switching the signals, I may understand enough of the issues now to try that again.
You can check the Resource Meter in Creator.