4 Replies Latest reply on Oct 6, 2017 7:57 AM by brsic_2235981

    IMO clock off by 30%

      I am using a PSoC 4 BLE in a new design, and the IMO clock is off by 30% (it's ~37MHz instead of 48MHz).   To prove this, I'm using a very simple design (pic attached) to output a divided down HFCLK (which by default is sourced from IMO).


      I would expect to see the output as HFCLK / 24 / 2 = 48MHz / 24 / 2 = 1MHz.  Instead I see (on a scope) ~768kHz.


      If I go into Configure System Clocks, and change the source of HFCLK to ECO (24MHz), then I would expect to see HFCLK / 24 / 2 = 24MHz / 24 / 2 =  500kHz.  And that's exactly what I see.


      So, ECO looks spot on at 24MHz, but IMO is about 37MHz.  And BLE, which runs on ECO, is working.  But UARTs, which run off IMO, are not working at the right frequency.


      I have not tried swapping hardware, as I don't have another board available just yet.  But this same exact design works correctly on the CY8CKIT-143A module, which has the CY8C4248LQI-BL583 (same part I am using).


      Question: The TRM discusses the CLK_IMO_TRIM2 for coarse setting the IMO frequency (3-48MHz).  I have the setting in Configure System Clocks for IMO at 48MHz (which I suspect corresponds to the TRIM2 reg).  But I see no detailed information on the TRIM1 register or PWR_BG_TRIM4/5 registers.


      Can I retrim an IMO that's that far out of wack?  Is this fixable via registers, or do I have a bad part?