8 Replies Latest reply on Aug 22, 2017 4:45 AM by JacobLerenius

    PSoC 5LP Sequencing SAR ADC

    JacobLerenius

      I have encountered an issue where the value from the precious channel affects the next value in the Sequencing SAR ADC. It appears that the settling time after the mux has changed the input, has a longer settling time than the time before the next ADC sample.

         

      My settings: The clock range is set to be between 1-18MHz and the issue exists over the entire range but is lager closer to 18MHz. I'm using external Vref (2.5V reference voltage), "0.0 to 2.048 (Single Ended) 0 to Vref*2", internal clk, hardware trigger (from pwm).

         

      How to replicate: add a SAR seq object, connect some channels (IOs) and set the voltage to high, low low low (from the bottom). Check the result. I get some thing like 1000-60-4-0 (should be 1000 - 0 - 0 -0) about 6% of the previous value is added to the next.

         

      Also, I read that the Vrefhi-out is the ground reference and when looking at the Analog routing it looks like it is going from the SAR into the SAR. Not much in the documentation regarding this critical signal. I assume one would like to connect it to AGND. It can be done in the analog routing, but I assume there is an API for this. I can't be the only one wanting to ground the negative input to the ADC.

         

      /Jacob

        • 1. Re: PSoC 5LP Sequencing SAR ADC
          user_1377889

          Can you please post your complete project so that we all can have a look at all of your settings. To do so, use
          Creator->File->Create Workspace Bundle (minimal)
          and attach the resulting file.

             

           

             

          Bob

          • 2. Re: PSoC 5LP Sequencing SAR ADC
            user_342122993
                    Jacob, To reduce channel crosstalk with muxed SAR_ADC, sampling time must be longer than input RC, Option 1 is to slow down acquisition or add terminating resistors on each input (~100 oHm @1MHz should reduce crosstalk to about 1%). Option 2 is to interleave channels: double the amount of input channels and terminate input of each second channel to the ground. Discard readings from the terminated channels. Sampling the ground will discharge SAR_ADC input capacitor thus reducing crosstalk, in expense of slower sampling rate.   
            • 3. Re: PSoC 5LP Sequencing SAR ADC
              JacobLerenius

              Thanks for the reply Bob. Our project can't be posted here and is really a large one so I'm no working on making a simple project where this issue can be seen.

              • 4. Re: PSoC 5LP Sequencing SAR ADC
                JacobLerenius

                Hi Odissey, thanks for your reply. As the sequencer is using the internal connections in the chip, adding a resistor on my input may slow down the charging of this capacitance and may give me too low values. The critical point is that it is not being charged/discharged fast enough before a sample is taken. I will check if changing the LP filter on our board will improve the situation. the resistor may be too large, resulting in to slow charging of the ADC capacitance.

                • 5. Re: PSoC 5LP Sequencing SAR ADC
                  user_342122993
                          Yes, Option1 price is that signal source has to be of low impedance, e.g. buffered. Option 2 is safe choice.   
                  • 6. Re: PSoC 5LP Sequencing SAR ADC
                    JacobLerenius

                    Created a project that sends the ADC data over USB. ch0 should be high and the other channels low. We use LP filters with 10k resistors (we need to keep current consumption down on amplifiers the have protection diodes). I measured by grounding the signal just before the PSOC (after the LP filter) and still got some channel leakage (2025 on ch0 gave me 6 on ch1) But this is much lower than with the LP filter. Are there some numbers on the capacitance on one can expect from the pin to the AD converter once the Mux has switched to a new channel? And what is the expected time between the PSoC finishing the muxing and the start of AD conversion?

                       

                    By the way, another question. is there a way to ground Vrefhi_out? Even if a GND is shown in she schematics, there is no connection between the signal and GND in the Analog routing page.

                       

                    Best regards, Jacob

                    • 7. Re: PSoC 5LP Sequencing SAR ADC
                      JacobLerenius

                      I added some more input to Bobs message above. When applying a hard ground to the PSoC pin I still had some "channel leakage". I was thinking about combining a lower resistance LP filter with the option 2 you describe. The problem is that I will not get correct readings if it can't ramp up the voltage fast enough after the ADC has been discharged. I then though about connecting each channel twice instead and reading every second value. However, it is not possible (in a straight forward way) in PSoC creator to connect the same pin to two inputs. Or do you have a suggestion on how to get round that issue?!

                      • 8. Re: PSoC 5LP Sequencing SAR ADC
                        JacobLerenius

                        The root cause is related to the input capacitance of the ADC. As an RC filter will have a lower bandwidth that the sequencer, the filter cannot be used to charge the internal capacitance fast enough. 2 options on solutions, active filter or Cf>>Cadc. In both solutions, the internal ACD capacitance must get charged/discharged fast enough. May help someone else struggling with the same issue.

                        //Jacob