Can you use UART debug prints and check if you are getting any DMA errors.
Btw, what is the PCLK frequency you are using?
There should not be any failure/halt in transferring data from GPIF to USB side, even we change the data on FPGA Side.
The following details are required to debug this issue.
1. What is application that you are implementing on high level, no need to tell actual application?
2. What is the change that you are doing in real-time on FPGA side? Changing the PCLK Frequency, SLWR, SLRD or any other?
3. What is the DMA Buffer size, count and DMA Channel type of DMA Channel from GPIF to USB and USB to GPIF
4. What is the exact number of bytes that USB Collected? Here, are you doing data transfer from Host PC to FPGA, since you told USB collected dozens of packets and stopped?
Any other details, which can help in understanding the issue clearly.