6 Replies Latest reply on Sep 14, 2017 8:06 PM by odissey1

    0-500khz Very Low Frequency direct sampling SDR, newb could use tips on what is and isn't possible with a PSoC5.


      I am in the process of designing an SDR primarily targeted towards Radio Astronomy, sat com, and other very weak signals. The idea is to build an HF direct sampling receiver with a 210/MSPS 16bit ADC pipe, that can decimate down to 1MSPS, and then mix 400-415mhz and 1-2ghz down to HF. Im pretty confident as far as the RF design and most of the hardware goes but I haven't really done DSP code. I just ordered an Analog Devices Pluto SDR, which uses a Zynq as its main dsp/cpu, and am excited to play with that because I no nothing about FPGA, im not even sure if I want one in my project.


      Anyways I have a few PSoC4 and 5 kits around, and I started thinking the PSoC5 has a 1MSPS ADC, and a bunch of other cool blocks to play with. I bought a bunch of the PSoC4/5 kits along with a Pioneer a while back because they looked pretty darn cool, and seem highly capable of building nice test and measurement tools. I ended up never using them because SDR and RF/Microwave projects took over all the other stuff I wanted to do. So I really don't know much about programming these chips at all! Luckily I bought "PSoC5 LP Measurement Projects" on Amazon, and Cypress has a ton of cool resources. Im also not a newb when it comes to programming micros in C or making schematics :)!


      So I think maybe a miniature SDR project is a good place to start, before I throw all these expensive ADCs, and RF components on to a PCB and end up picking something for DSP and Data Transfer on a Whim and the put it together and realize I hate it because I had no idea what I needed at the time. I don't have any receivers digital or analog that receive Super/Very/Extra Low Frequency, not only are they neat for listening to submarine communications and standard time signals around the world, but a lot of solar astronomy uses VLF.


      So my idea is that I can connect an active whip antenna meant for 0-1mhz to the ADC, and then hopefully duplicate the signal in to an I and Q then shift the Q by 90 degrees using all hardware blocks. From there I can hopefully implement any decimation. filtering and modulation in the cpu, along with generating an FFT plot, maybe im asking to much of the micro... Since we are only sampling 1MSPS and we only care about 5Khz of the sample after that, I would assume the Hi Speed USB (12Mbit right?) should be fast enough to stream the IQ samples to the PC along with FFT plot data. I know making an FFT on the chip and sending it to the PC along with the IQ samples seems pointless, but I like the fact you can do things really fast an easy by piping the FFT points in to something like GnuPlot or Excel... that may be all the info you need sometimes.


      So does this project seem feasible, or am I asking to much of the PSoC chip? Should there be enough digital blocks to at least do the IQ mixing? Not knowing much about CPLD or FPGA, im always curious just how big of a chip I would need to pick for a real SDR like the one I have in mind. I am actually kind of hoping when I build the bigger one that I may be able to do a lot of actual DSP on something like a ~200mhz+ micro or CPU like an xmos or cheap all winner a10 and then stuff a cypress usb3fx or gigabit ethernet controller on the SDR to get the data to the PC.

        • 1. Re: 0-500khz Very Low Frequency direct sampling SDR, newb could use tips on what is and isn't possible with a PSoC5.


          I apologize for PSoC forums being completely screwed by the latest update. You may find several threads discussing SDR radio projects. See liks below:



          Simple Radios


          Attached are description of the SDR radio using Tayloe detector and PSoC3 (PDF and project code). With small effort it can be ported to PSoC5. The project can be greatly simplified if using external DDS chip to produce carrier frequency.


          While working with PSoC micro is a lot of fan, I am sure that you familiar with low-cost RTL-SDR usb dongle (http://www.rtl-sdr.com/ ) and various downconverters for it to cover 0-20 MHz range. This might be a safe alternative if you want to get down to the root by skipping the hardware design fun.

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          • 2. Re: 0-500khz Very Low Frequency direct sampling SDR, newb could use tips on what is and isn't possible with a PSoC5.

            If 0-500kHz is all you need, then simple DDS32 generator can produce quadrature signals for direct sampling:

            How can I handle a PSoC 5 community library DDS24 on PSoC 4 BLE device ? 


            Instead of the external Tayloe detector you may try to use PSoC internal modulators (4 avaialble), which also work in 0-500kHz range.

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            • 4. Re: 0-500khz Very Low Frequency direct sampling SDR, newb could use tips on what is and isn't possible with a PSoC5.

              Sorry I didn't know this thread ever got replied too! Since the last time I posted I have done a bit more research, and have a few more questions. I have already looked in to most of the other psoc sdr projects which has been helpful. I have been busy working on a GPSDO/Quadrature Modulator so I haven't actually started experimenting with my psoc5 and sdr idea yet. But I dont want to get half way down the path in my head just to realize its impossible. I do know about other options, and own plenty of SDR equipment, this project is a stepping stone for my knowledge though, I have a few 105 16MSPS ADC's I want to use to make a DDC sdr  with. Yes I could use a mixer to upconvert the VLF/ELF bands for my AirSpy, but then I will still have no idea how the DSP/Code side of an SDR works.


              So here is my idea, Im thinking I could use two PSOC5 mixer's and a 90 degree phase shift to make the 1-500khz Quadrature Detector right on the chip, and then use the built in opamps between the QSD and the 12bit 1MSPS ADC. So basically all I will need to do is plug in the antenna and I wont have to worry about building any RF hardware, because it is all in the PSoC5. Luckily 500khz is such a small amount that I can also use the full speed USB to send all of the sampled spectrum to the PC. Depending on the SDR either an FPGA would be doing all the DSP based alias filtering and Decimation, or the is the whole lot of sampled IQ data transferred to the PC to take on the DSP work. Now here is where I get a bit hazy, I know an arm cortex f4 with DSP can do all the filtering and decimation all the way through the AM band, based on another SDR project I have read up on. The PSoC is only a cortex 3, but i has the ability to run Verilog and it has a DSP block. Would these be able to do the cic and fir filtering along with bandwidth decimation, down to maybe 10khz of bandwidth? I would love to be able to keep all this stuff in the PSoC5 extras for the most part, that way I can use the cortex mcu to run an LCD with FFT/Waterfall and do a few different types of demodulation that would be useful in these lower bands, this way you don't actually need to plug it in to a computer if your out and about.Kh

              So is this asking too much of the chips capability?


              I sure hope not, it seems like a ton of stuff for a micro to handle, but on the other hand it is only 500Khz of bandwidth that needs to be processed. Im looking at this as a really good way to learn more about SDR programming in general and a more simple taste of using digital logic to process ADC samples.

              • 5. Re: 0-500khz Very Low Frequency direct sampling SDR, newb could use tips on what is and isn't possible with a PSoC5.

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                2. Well it is apparently possible (PSoC3 project was attached above). I made a screenshot of the schematic page, and there is nothing special, see picture attached. Basically, ADC samples HF signal downconverted using external Tayloe detector, and passes it through the Filter block, that's all. 


                3. The Tayloe detector is very cheap (~$0.50) and proven to work. On the contrary, using direct sampling with 16 MHz ADC is quite expensive (~$10/pc), and will require HF amplification before sampling. The question is how are you going to process 16 MHz/ch data stream? This is a job for FPGA or DSP.


                4. There is a reason why the external demodulator is used. The incoming signal is very weak (uV range), so the digital noise in PSoC will kill it. Notice a high-quality Opamp after the demodulator. PSoC does have internal modulator and Opamp, but their quality are subpar, as compared to the external parts provided on the schematic. I would try external parts first, then compare to internal.


                5. Simple way to produce IQ signals in 0-20MHz range is to use PSoC-based DDS generator (DDS24). See link:

                DDS24: 24-bit DDS arbitrary frequency generator component 



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                • 6. Re: 0-500khz Very Low Frequency direct sampling SDR, newb could use tips on what is and isn't possible with a PSoC5.

                  I upgraded and recompiled Mike's Hightower the SimpleSDR project for PSoC5LP (KIT-059). The project is not tested, to become a radio receiver it will need associated hardware parts (basically, a Tayloe mixer and Opamp. See original schematic and manual for details.

                  Though seemingly a simple project dating back to 2010, it is is a marvel of EE design, incorporating in single PSoC several non-trivial concepts, such as fractional PLL design, IQ demodulation using Hilbert filter and adjustable digital Filter coefficients. Judging from the professional design and extra location clue (Tucson, AZ), I am guessing that M. Hightower is  probably a Raytheon engineer.