1 Reply Latest reply on Apr 24, 2017 10:19 AM by MichiyukiY_91

    Random questions - RTC, PCM/PDM, DAC, ADC, etc


      1 - The customer has a requirement on the RTC to drift less than few minutes per year, this translates into 2 ppm error. Is there a way to run the RTC with this accuracy? if yes, how?


      2 - The customer wants to use PSOC6 in a headset for audio application, how can you synchronize an external DC/DC converter with the audio clock?


      3 - PSOC6 has a built in regulator, the customer is concerned about noise coming from the regulator to the audio, do we have any data on the noise characteristics of teh regulator?


      4 - How do we tune the crystal for optimum accuracy, this is related to question #1?


      5 - Need more data on the DAC, we heard it is a voltage DAC vs. current DAC, What is the maximum speed that we can run the DAC at? The customer is asking for 4MSPS.


      6 - Need more information on the energy profiler and the e-FUSE. How does it work? Is there a way to see how many times a counter or code was being accessed?


      7 - Do we have I2S slave code for UDB? The customer has implemented a I2S slave in UDB in PSOC4, it seems to take a lot of space, do we have anything better?


      8 - What is the resolution and decimation filter on the PCM/PDM? Can we do 48 bit?


      9 - Does the RTC run in hibernate mode? What is the current consumption?


      10 - How to buffer instructions in cache if it is greater than 8KB?


      11 -What is the maximum clock speed for PCM/PDM?


      12 - Can ADC conversion be done while sleeping?


      13 - Can we configure a GPIO in a certain state before hibernate?


      14 - The customer wants to use the ADC to detect an activity and wake up the chip, Can this be done? Do we have any solid power estimates?


      15 - (Related to previous questions) - Is there a way to run the ADC in PSOC 6 in deep sleep wake up every so often detects if there is audio and then wake the system up?

        • 1. Re: Random questions - RTC, PCM/PDM, DAC, ADC, etc



          Below are answers to your questions, but there are a couple questions I need more feedback on to reply clearly:


          1 & 4. As per the PSoC 6 datasheet, the frequency tolerance of WCO is 50ppm for a 20-ppm crystal at 25 degree Celsius. There is an option to trim the 32-kHz oscillator to within 2 ppm using a higher accuracy clock.


          Absolute crystal accuracy: This occurs because the crystal itself oscillates slightly faster or slower due to imperfect manufacturing. This error is typically in the ± 25 ppm range for common crystals, i.e. an error of ± 1 minute per month. By measuring and then correcting for the error of a given WCO device the error can be reduced, for e.g. to 1 ppm or ± 32 sec per year. This calibration must be done once per board (chip + crystal) with an extremely precise time reference, such as an atomic clock or calibrated lab equipment.


          Temperature dependency: This occurs because crystals have a well-known and significant temperature dependence. This can be optionally dynamically corrected based on a temperature measurement and firmware-calculated calibration settings.


          2. Can you please elaborate on this requirement? I was not able to understand this clearly.


          5. PSoC 6 has a 12-bit Continuous Time DAC (CTDAC) apart from the 7-bit and 8-bit IDACs which are available as part of the CapSense blocks. The settling time for the CTDAC is 2us for a 25-pF load (which translates to 500ksps).


          6. The PSoC 6 Technical Reference Manual (TRM) will have a dedicated chapter on this. It will be posted in the coming weeks, so please refer that when posted.


          7. In PSoC 6, we are planning to have a fixed function I2S slave.


          8. The PDM can produce word lengths from 16 to 24 bits at audio sample rates of up to 48 ksps. Can you please let me know what you meant by decimation filter? We do have something called decimation rate, which is in range of 0 to 254.


          9. Yes, the RTC is part of the backup power domain and is independent of the PSoC 6 power modes. That means, the RTC will continue to operate as long as the backup domain is powered regardless of the power mode (Active/Sleep/Hibernate) of PSoC 6.


          10. Instruction buffering is part of the device architecture itself and is taken care internally. Can you explain more on this requirement?


          11. The PDM supports a maximum clock speed of 3.072 MHz.


          12. Yes. In sleep mode all peripherals except CPU are available.


          13. Yes. The GPIO states are frozen during Hibernate. The firmware can make the GPIO high/low before transitioning to the Hibernate.