Below are answers to your questions, but there are a couple questions I need more feedback on to reply clearly:
1 & 4. As per the PSoC 6 datasheet, the frequency tolerance of WCO is 50ppm for a 20-ppm crystal at 25 degree Celsius. There is an option to trim the 32-kHz oscillator to within 2 ppm using a higher accuracy clock.
Absolute crystal accuracy: This occurs because the crystal itself oscillates slightly faster or slower due to imperfect manufacturing. This error is typically in the ± 25 ppm range for common crystals, i.e. an error of ± 1 minute per month. By measuring and then correcting for the error of a given WCO device the error can be reduced, for e.g. to 1 ppm or ± 32 sec per year. This calibration must be done once per board (chip + crystal) with an extremely precise time reference, such as an atomic clock or calibrated lab equipment.
Temperature dependency: This occurs because crystals have a well-known and significant temperature dependence. This can be optionally dynamically corrected based on a temperature measurement and firmware-calculated calibration settings.
2. Can you please elaborate on this requirement? I was not able to understand this clearly.
5. PSoC 6 has a 12-bit Continuous Time DAC (CTDAC) apart from the 7-bit and 8-bit IDACs which are available as part of the CapSense blocks. The settling time for the CTDAC is 2us for a 25-pF load (which translates to 500ksps).
6. The PSoC 6 Technical Reference Manual (TRM) will have a dedicated chapter on this. It will be posted in the coming weeks, so please refer that when posted.
7. In PSoC 6, we are planning to have a fixed function I2S slave.
8. The PDM can produce word lengths from 16 to 24 bits at audio sample rates of up to 48 ksps. Can you please let me know what you meant by decimation filter? We do have something called decimation rate, which is in range of 0 to 254.
9. Yes, the RTC is part of the backup power domain and is independent of the PSoC 6 power modes. That means, the RTC will continue to operate as long as the backup domain is powered regardless of the power mode (Active/Sleep/Hibernate) of PSoC 6.
10. Instruction buffering is part of the device architecture itself and is taken care internally. Can you explain more on this requirement?
11. The PDM supports a maximum clock speed of 3.072 MHz.
12. Yes. In sleep mode all peripherals except CPU are available.
13. Yes. The GPIO states are frozen during Hibernate. The firmware can make the GPIO high/low before transitioning to the Hibernate.