I'm developing a BLE peripheral that has to go in deep sleep and keep connecting to a central device using CY8C4247FNI-BL483 and I'm switching from a "developing" board to a miniaturized board for production. Loading the same firmware on both boards I see that on the developing board everything works fine. On the production board I find that the peripheral device connects to the central, it negotiates successfully for a longer connection interval (500 ms with a 5s supervision TO and slave latency to 0) with the central, tries to go on deep sleep and, after supervision TO period has passed, the central device receive a "Connection Terminated Notification" event and the connection goes down. As a central device, for testing purpose, I'm using "CY5670: CySmart USB Dongle" and CySmart. I've noticed that if the BLESS doesn't go in deep sleep it maintains the connection up without any trouble.
The main differences between the two board versions are:
1-Different antenna routing network.
2-Different microcontroller package (from QFN to WLCSP)
3-Different layout and component dimensions for the WCO and ECO crystals involved.
I think the difference at point number 1 is not the the probable cause of the issue otherwise I will see connection problems even if the device doesn't go in deep sleep. Reading some Cypress application notes (AN92584 and AN95089 in particular) seems that all the clues lead to a WCO inaccuracy that may cause an improper connection timing between the devices. In fact even if the WCO crystal capacitors have the same values between the two board versions, these capacitors have different aspect ratio (they're smaller on the production board and the crystal is smaller also) and the layout of the connection between the crystal and the microcontroller is significantly different for the two boards. In production board the microcontroller and the crystal are put in different layers (top and bottom) of a 4 layers PCB and connected through VIAs. The inner layers are for VDD and GND. Could this be the problem? Should I have to "tune" the WCO crystal capacitors because the layout adds too much parasitic capacitance and this drifts significantly the WCO from the nominal value? Since the capacitor tuning operation is quite difficult for us to accomplish I would like to be pretty sure for this to be the possible issue cause before trying to operate in that way. In fact, if possible, a firmware workaround is preferable. By the way, is there a possibility to track this eventual issue somehow on the firmware by some BLE stack calling or system calling? CyBle_Start() returns "CYBLE_ERROR_OK".