3 Replies Latest reply on Mar 21, 2017 6:56 PM by msur

    PSoC6 capabilities

    user_473032933

      Hi,

      I would like to ask if PSoC6 supports the following.

       

      1. Can we use the PLDs in the Universal Digital Blocks in order to fit a hardware multiplier?
      For example, in PSoC4, I could fit a 3x3 bit hardware multiplier using the PLDs. Could we support a 16x16=32bit hardware multiplier in PSoC6's PLDs?

       

      2. Can we access chip's RAM from verilog when we design a custom PSoC6 component?

       

      3. The PSoC4 has the CyBle_SetTxPowerLevel() function to change the transmission power level. The input parameter configures power from -18db to +3db. What are the options in PSoC6? Can we configure the transmission power at -80db for example?

       

      Best Regards,

      Yiannis

        • 1. Re: PSoC6 capabilities
          iym

          Hello,

          Apologies for the late reply:

           

          1. It should be possible but we have not done any implementation to comment on the width of the multiplier that can be implemented using 12 UDBs. It has 3 times as many UDBs as in PSoC 4. So if a 3x3 multiplier was implemented using PSoC 4, an 8x8 is definitely possible. 16x16 will depend on the resources required.
          2. Unfortunately we cannot access the chip RAM from Verilog. However, you can use FIFOs and registers, which can be loaded from RAM using firmware/DMA. This sort of provides some indirect access to RAM.
          3. The options in PSoC 6 vary from -20 dBm to +4 dBm.
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          • 2. Re: PSoC6 capabilities
            user_473032933

            Thank you very much for your answer.

             

            PSoC does constitute a spectacular architecture.

            My opinion is that it is a ground-breaking chip and PSoC6 consumption capabilities renders it one of the most attractive solutions.

            I would like to deepen this discussion.

            1. Regarding hardware multiplier, even if an 8x8 multipler can fit, this would use the overall of the macrocells so that other circuitry that requires UDBs perhaps could not fit. It is very powerfull to have a second multipler in the chip (the first is in the CPU). Are there any plans that the Digital Filter Block that PSoC5LP includes can be implemented also in PSoC6?

            2. processing it...

            3. In our app, the transmission power is required to be as low as -80db in some cases. Is there any option the internal RF Power Amplifier can be switched off so that we could reduce the transmission power? Will this be supported in PSoC6?

             

            Best Regards,

            Yiannis

            • 3. Re: PSoC6 capabilities
              msur

              Yiannis,

               

              My answers -

              1. I agree but just to give a quick picture of PSoC 6 - it includes 2 cores both capable of performing single cycle multiplication (so you already can perform two multiplications in any given cycle). In addition you get 32 TCPWM(timer/counter/PWM/quad decoder) blocks, 9 Serial communication blocks (I2C/SPI/UART), one I2S block, one PDM-PCM block, one HW crypto block and 2 SmartIO blocks, so the 12 UDBs can very well be used for custom logic like multiplication in your case. Currently, we do not plan to support PSoC 3/5's DFB in PSoC 6.

               

              3. No, at the moment we do not support switching off the Tx PA.

               

              Regards,

              Meenakshi Sundaram R

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