Clock accuracy is not within the specified tolerance range

[KaAu_4610386]

Greetings,

My project has a warning (see below) saying that the clock accuracy is not within the specified tolerance range. What are the implications of this warning? Any suggestions on how to fix it?

Thanks in advance!

[VenkataD_41]

Hi,

Are you using ILO in your application? If yes, this is expected because the tolerance of ILO has high tolerance in case of PSoC.

Can you please attach your project once?

Thanks

Ganesh

[Len_CONSULTRON]

KaAu,

As Ganesh pointed out, your Clock_6 is sourced by ILO which does not have a tight tolerance (-55% to +100%).  However the clock component by default has a +/- 5% tolerance as a clock check.  (See items in RED in the "Configure 'Clock'" dialog.)

To 'fix' this you can:

• uncheck the "Tolerance:" box.  This will not perform a clock tolerance check on this clock.
• Change the '-' and '+' tolerances to mix the source clock tolerance.
• Change the "Source:" to a more accurate clock like MASTER_CLK. 

The warning can be ignored if this clock and all it drives is not critical to be accurate.  For example, a slow clock like ILO can be used for switch debouncing. 

Len

[odissey1 · Accepted solution]

KaAu,

In your project, the MASTER_CLK is 48MHz, and the Clock_6 is set to 50Hz, 5% accuracy, and Auto selection. The 50Hz, can't be obtained from the MASTER_CLK, because max divider value is 2^16=65536. So the lowest frequency obtainable from the MASTER_CLK is 48MHz/65536 = 732.4 Hz. Therefore PSoC automatically selects low-frequency ILO oscillator, which was set to 100kHz. The ILO has much lower accuracy (-55+100%), than you requested (5%).

The solution is to change Clock_6 source to MASTER_CLK, and set its value e.g. to 1000Hz, and to add a Divider component with divider value 20, to obtain final value of 50Hz.

/odissey1