14 Replies Latest reply on Nov 19, 2020 8:06 PM by JayakrishnaT_76

    Gpif  master

    lfl_4816136

      Hello there

      I designed an 8bit master state machine with GPIF design tool. I want to control the state machine to send data to the outside. This data may be a fixed data or a changing data. Now I have some problems.

      1 How should I set the DMA channel? P2U? P2S? or others, I have seen some examples, but none of them seem to meet my needs

      2 How can I generate data and send it out? Are there related API functions?

      Here is a screenshot of the state machine I designed

      Can you give me some suggestions, I look forward to your reply

        • 1. Re: Gpif  master
          JayakrishnaT_76

          Hello,

           

          Please let me know if you have referred to AN87216 which describes about designing a GPIF II master interface to communicate with an external synchronous slave FIFO. The link to the same is given below:

          https://www.cypress.com/documentation/application-notes/an87216-designing-gpif-ii-master-interface

           

          In this project, the data obtained from the USB socket is transferred to the GPIF socket and is sent out to the slave device. That is the DMA channels are between U Port and P Port. I understand that this is not the interface that you are looking for. But you can refer to this project and modify your project for your requirement.

           

          Please find my comments for your questions below:

          1. Please let me know what is the source of data? Is it the USB port? If yes, then the DMA channel is to be created between U Port and P Port.

          2. Can you please elaborate this requirement so that I can understand it better? Do you mean to say that the data should be generated and not obtained from any other blocks? And this generated data needs to be sent out?

           

          Also, can you please share the interface timings so that we can check if the state machine that you have shared in your query is proper or not?

           

          Best Regards,

          Jayakrishna

          • 2. Re: Gpif  master
            lfl_4816136

            hello

             

            It may be that my problem is not described clearly. As you think, the function I want to achieve is to continuously send 8-bit data to my external device internally. This data is a constant or variable defined by myself, such as data 8. Or 1, 2, 3, n..., that is to say, what I consider now is to only send data to external devices

            • 3. Re: Gpif  master
              lfl_4816136

              The 8-bit GPIO data bus of the state machine is not connected to usb or sib, but the 8-bit data bus of a DA chip. Now I want to send data to it internally for a verification

              • 4. Re: Gpif  master
                lfl_4816136

                 

                Here is a screenshot of the timing and action settings

                • 5. Re: Gpif  master
                  JayakrishnaT_76

                  Hello,

                   

                  According to your state machine, the following will happen:

                  1. Initially, the state machine will move from START to STATE0. It will drive 8 bit data there.

                  2. Then, it will undergo a transition to STATE1. Here it will drive 8 bit data and a GPIO.

                  3. Then again it returns back to STATE0. This cycle repeats.

                   

                  But when DR_DATA is used in a state, the GPIF socket associated with it should have some data to drive to the external device. If this is not satisfied, then errors will occur. So, I have modified your state machine and the modified state machine and created an example project for you. As per my understanding you just want to transfer data from the GPIF II block to the DA chip. In the project that is attached in this response, the data to be transferred to the DA chip through GPIF II block of FX3 comes from the host through the USB port. With this implementation, it is easy to customize the data that you want to send through the GPIF II block to the external device. The flow is shown below:

                   

                  Host (control center application) -> USB socket -> GPIF II socket -> External device (DA chip)

                   

                  The data transferred from the host is stored in a DMA buffer and is transferred out through the GPIF II block. Steps to do a quick test is given below:

                  1. Build the project and program the .img to RAM using Control Center Application.

                  2. Select the OUT endpoint as shown in the snapshot below and Enter the Data to Send. Here, Iam transferring 1 byte data (0x12). You can change it if required.

                  3. Press Transfer Data-OUT. This will transfer the data to the U Port and send it to the GPIF II socket. The state machine is designed in such a way that a GPIO acts as a strobe signal while the data transfer happens.

                   

                  You can send multiple bytes from the Control center application. The strobe signal remains active (HIGH) one clock cycle before transferring first byte and remains HIGH until the DMA transfer is complete. When the strobe signal goes LOW, the data should not be sampled by the external device. A logic analyzer capture while transferring the data 0xA5 is shown below.

                   

                  The strobe signal is captured in channel 11.

                   

                  You can make modifications on the GPIF II project to meet the interface timings properly. The interface clock is around 96MHz for this project. If you want to adjust it, then changes are to be made on firmware. Please let me know if this is required.

                   

                  Please let me know if you have any queries on this.

                   

                  Best Regards,

                  Jayakrishna

                  • 6. Re: Gpif  master
                    lfl_4816136

                    Hello there,

                    First of all thanks for your reply

                    According to your reply, Host (control center application) -> USB socket -> GPIF II socket -> External device (DA chip)

                    1. Can I directly write data to the DMA Buffer or GPIF II socket through the FX3 firmware and then send the data to the external device? If so, how can I achieve it?

                    2. According to the state machine you provided, I made some modifications in the GPIF design tool, but it seems that my timing requirements cannot be achieved. The following is a timing diagram of DA chip data transmission:

                    3. Before sending data to the DA chip, it is necessary to configure the DA registers. I use GPIO to simulate spi to configure the DA. Is this okay?

                    I look forward to your reply。

                    • 7. Re: Gpif  master
                      lfl_4816136

                      Or is it possible to abandon the GPIF state machine and directly use GPIO to send data to DA?

                      • 8. Re: Gpif  master
                        JayakrishnaT_76

                        Hello,

                         

                        Please find my comments below for your questions:

                        1. Yes, it is possible to fill the DMA buffers in the firmware and send it out through the GPIF II block. Please find the attached project where I fill one byte(0x12) in DMA buffer and send it out through the GPIF II block. Please note that I have not changed the state machine from what was shared before. This state machine will not meet your timing requirements. If you want to keep on transferring one byte, then please uncomment following line

                         

                        //tcplt = CyTrue;

                         

                        in the DMA callback function AppDmaCallback(). This project enumerates the same was as the project that was shared before. But the DMA channel is between CPU socket and GPIF II sockets and not between USB socket and GPIF II socket. One byte will be sent automatically once the device enumerates.

                         

                        Please find the snapshot of logic analyzer capture below:

                         

                        2. Regarding the interface timings, according to my understanding, the data needs to be driven at the positive and negative edge of the clock. Also, at the 2nd falling edge of clock, both data and a sync signal needs to be driven. Please let me know if my understanding is correct. Otherwise, please let me know the correct sequence.

                        Also, I found that 10 bit data bus is shown in the timing diagrams but in your description, you mentioned 8 bit data bus. Please confirm this also.

                         

                        3. Please let me know why you are not using the SPI lines for configuring the registers of the DA chip. Bit Banged GPIOs can be used as SPI lines but the SPI timings are not guaranteed in this usage. You can refer to the following SDK example to understand how this can be done:

                        C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\serialif_examples\cyfxusbspigpiomode

                         

                        4. Regarding the question "Or is it possible to abandon the GPIF state machine and directly use GPIO to send data to DA?", this cannot guarantee the synchronization between the parallel data. Please let us know what is your interface clock requirement. Also, please elaborate your final application. Please provide more information on your application so that we can suggest the best possible solution.

                         

                        Best Regards,

                        Jayakrishna

                        • 9. Re: Gpif  master
                          lfl_4816136

                          Hello there,

                          I read your reply, first of all about your question:

                          1. Your understanding of the timing of the DA chip is correct, and my state machine only uses 8-bit data bus because the hardware design only uses 8-bit data, and the DA clock frequency is 25M

                          2. The SPI line is not used because the spi line is connected to spi_flash, so I can only simulate spi through GPIO

                          3. Regarding your fourth reply, if GPIO cannot guarantee parallel data synchronization, then it can only be achieved through a state machine

                          Can you give me some suggestions on the design of the state machine

                          • 10. Re: Gpif  master
                            JayakrishnaT_76

                            Hello,

                             

                            Please find my comments below:

                            1. Even if the SPI lines are used for communicating with the flash, the same lines except SSN can be used for communicating with a different device also. You need to use another GPIO for SSN signal only. This can be used if you have not hard wired the SPI lines to the flash alone. If the SPI lines can be connected somehow to the DA chip, then an additional GPIO is only needed for SSN.

                            2. Please find the attached project. Once the device enumerates with this firmware, it will send out 8 bytes once (repeated 0x12 and 0x21). For sending the 8 bytes repeatedly, please uncomment the following line as mentioned in my previous response:

                             

                            //tcplt = CyTrue;

                             

                            GPIO 0:7 acts as data bus and GPIO_28 provides the sync signal. Please probe the lines and check if the timings are okay or not. The interface clock is set to 27MHz in this project.

                             

                            Best Regards,

                            Jayakrishna

                            • 11. Re: Gpif  master
                              lfl_4816136

                              Hello, according to your reply, I read the timing waveform of the state machine in the attachment. I have some questions. First of all, you pass CyU3PPibClock_t pibClk = {15, CyFalse, CyFalse, CY_U3P_SYS_CLK} will always be set to 27M, right

                              Then regarding the timing of the state machine, as you said earlier, the data needs to be driven at the positive and negative edge of the clock. Also, at the 2nd falling edge of clock, both data and a sync signal needs to be driven.But the waveform I see seems to be different

                              It doesn’t seem to meet the timing requirements I need just to see through the state machine. Did you make the corresponding settings in the FX3 firmware? If there is any, can you mark it?

                              • 12. Re: Gpif  master
                                JayakrishnaT_76

                                Hello,

                                 

                                Please do not use the timings generated by the GPIF II Designer tool for checking the interface timings. Please probe the lines physically using a logic analyzer to capture the signals. The modifications done on the project are mentioned below:

                                 

                                1. Changed the PIB clock to 27 MHz by using the following line of code:

                                CyU3PPibClock_t pibClk = {15, CyFalse, CyFalse, CY_U3P_SYS_CLK};

                                 

                                2. The PIB DLL parameters were set by using the function CyFxApplnSetPibDllParameters(). Please refer to the following KBA to understand how the DLL parameters were set:

                                Configuring EZ-USB® FX3™ GPIF-II DLL - KBA210733

                                 

                                3. DDR mode was enabled for the GPIF II block by changing the CY_U3P_PIB_GPIF_CONFIG (in cyfxgpif2config.h) from 0x800087B0 to 0x800087F0.

                                 

                                4. The state machine was modified to satisfy your requirement.

                                 

                                Please find the logic analyzer captured screenshot at our end using this project below:

                                 

                                GPIO 17 is the interface clock and Channel 11 is the SYNC signal. Please probe at your end and let us know if the timings are okay or not.

                                 

                                Best Regards,

                                Jayakrishna

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                                • 13. Re: Gpif  master
                                  lfl_4816136

                                  Hello there,

                                  Thank you very much for your help. Your design already meets my timing requirements, but do you have a guidebook on how to perform logic analysis?

                                  When we design a state machine, can we only observe the actual timing situation through logic analysis?

                                   

                                  • 14. Re: Gpif  master
                                    JayakrishnaT_76

                                    Hello,

                                     

                                    The signals can be probed by using a logic analyzer like Saleae. The software can be downloaded from the following link:

                                    Logic analyzer software from Saleae

                                     

                                    You should be able to find the user guide from the following website:

                                    https://support.saleae.com/

                                     

                                    The snapshots shared in this thread were all captured using Saleae Logic. Also, it is recommended to probe the signals using a logic analyzer to observe the actual timing rather than looking into the timings provided by the GPIF II designer tool. This is because we have seen errors at times in the timings generated by the GPIF II designer tool.

                                     

                                    Best Regards,

                                    Jayakrishna

                                    1 of 1 people found this helpful