2 Replies Latest reply on Nov 23, 2020 11:52 PM by JaKr_4815161

    CY15B104QS Simulation Model QSPI




      I have a question regarding the verilog simulation model of the CY15B104QSN FRAM that I downloaded from https://www.cypress.com/documentation/models/verilog/verilog-vhdl-cy15b104qs


      According to the data sheet (https://www.cypress.com/file/400726/download) of the FRAM, the read command 0x03 should support QPI, see also the figure below from the datasheet.

      The the non volatile configuration register 2, Bit 6 is set to 1 (QUAD SPI). The simulation model recognizes my command correctly (command and address as well as dummy bytes send via all four lanes, QUAD Mode), however, the response of the model is send only via lane SO.


      After a look into the model verilog code, I saw that for Instruction READ, only SO is used (line 3800 of file cy15b104qs.v):


      DataDriveOut_SO  = data_out[7-read_cnt];


      while other instructions also use the SI, WP and Reset signal if QPI is set to one:


      DataDriveOut_RESET = data_out[7-4*read_cnt];

      DataDriveOut_WP    = data_out[6-4*read_cnt];

      DataDriveOut_SO    = data_out[5-4*read_cnt];

      DataDriveOut_SI    = data_out[4-4*read_cnt];


      Is this a flaw in the model or is it correct, that the instruction READ does not use all lanes in QPI mode in contrast to the figure in the data sheet?


      Best regards,