4 Replies Latest reply on Nov 24, 2020 1:53 AM by SudheeshK_26

    S25HS512T verilog model

    JuLe_4821041

      Hi,

       

      I have a problem when I do post gate level simulation(timing annotation) with S25HS512T verilog model.

       

      When a skew between 'SCK' and 'CSNeg' is larger than 1ns in Flash input boundary, Flash model drives SO continuosly eventhough 'CSNeg' is changed '0' to '1'.

      After then, SoC and Flash drive pad at the same time and this makes unknwon state in pad.

      So, I tried to add delay on 'SCK' and make skew smaller than 1ns, eventually I found test is passed.

      However when I see a datasheet, hold time requirements is 4ns.

      Therefore I think this verilog model is for just RTL simulation(no timing). Is it right?

       

      Thanks,

      Juyeon Lee.

        • 1. Re: S25HS512T verilog model
          SudheeshK_26

          Hello,

           

          Did you use SDF file for simulation? If not, please perform the simulation using SDF file and check if you are facing the same issue.

           

          Thanks and Regards,

          Sudheesh

          • 2. Re: S25HS512T verilog model
            JuLe_4821041

            Hi Sudheesh,

             

            Thanks for your quick response.

             

            Unfortunately, I missed sdf file for Flash model.

            I'm going to simulate again using sdf file and let you know if I have same problem again.

             

            Thanks,
            Juyeon Lee.

            • 3. Re: S25HS512T verilog model
              JuLe_4821041

              Hi Sudheesh,

               

              Connecting to this community is hard in my site. I have to try many times...

              So I asked further question by replying to your e-mail. Is it ok?

               

              Below is the contents of the mail I sent

              ========================================================

              Thanks for your quick response.

              I tried to simulate again using SDF for Flash model, but I have another problem.

               

              I have below warning message and it seems to SDF annotation has been failed.

              xmelab: *W,SDFDLM: Scope top.dut has delay_mode directive. Skipping IOPATH/Timing check annotation for scope top.dut.

               

              I think this problem was happend because your SDF has INSTANCE "dut" even though Flash model has no intance named "dut".

              So I think SDF has to be modified like right side in below capture. Right?

              I set the annotation scope to top of Flash model.

               

               

               

              Thanks,

              Juyeon Lee.

              • 4. Re: S25HS512T verilog model
                SudheeshK_26

                Hello,

                 

                I am not able to open the image that you attached with your previous response.

                Could you please attach it again?

                 

                Thanks and Regars,

                Sudheesh