By how much the results are off ? Could you provide more information about your settings ? The ADC configuration( input pins, acquisition time) all those details? Also set us know how the how you are updating flash ?
Here is a chart of ADC samples during a flash write. The flash write occurs right when the spike in the graph happens:
The ADC is configured in single-shot mode. A clock triggers a flip-flop which triggers an interrupt. The interrupt handler calls Cy_SAR_StartConvert(). The sampling rate from this set up is 2160hz. The ADC is configured for one single ended input with an achieved acquisition time of 560ns and no averaging. Vref is selected to be Vdda/2 and Vneg is set to be Vref. See screenshots below of the configuration.
The pin selected for the input is 10 if that makes any difference.
Thanks for your help.
I forgot to add details about flash. I am calling CyFlash_StartWrite() and then polling Cy_Flash_IsOperationComplete() until the operation is finished. This is happening on the CM0+, while all the sampling stuff is happening on the CM4. I have moved the location of this flash write to several different sectors, all with the same result.
What happens if you change the Vref select option from VDDA/2 to System bandgap? Reduce the voltage range of the input signal appropriately.
I had similar results using the system bandgap as the reference.