1 Reply Latest reply on Nov 11, 2020 8:34 PM by JayakrishnaT_76

    How to setting cx3config.cycx for YUV422_10 / 4 lanes

    IaLi_4435656

      Hi All,

           I am setting cx3config.cycx, but I get some problem. The error show " Parallel output cannot finish within 1 line. Use faster Output Pixel clock and/or wider H-blanking."

       

      20201110-01.JPG

       

      How do I resolve the problem?

        • 1. Re: How to setting cx3config.cycx for YUV422_10 / 4 lanes
          JayakrishnaT_76

          Hello,

           

          Please confirm that the input format is YUV422_10 bits and not RAW10 format.

           

          If you want to use YUV422_10 bits format, please try the following test:

          1. Change the Input video format in Image sensor configuration tab to YUY2.

          2. Use the same configurations in CX3 Receiver Configurations tab except CSI RX clock divider. Change this parameter to 4.

          3. Save the generated files.

          4. In the cyu3mipicsi.c file, change the first parameter to CY_U3P_CSI_DF_YUV422_10.

           

          Note that with this setting, CX3 will pad 6 0s along with the incoming 10bit data and sample it as 16bit data. The host application needs to be modified to remove the padded 0s to reconstruct the pixel data. The next 10bits will be present in the next sampled 16 bits.

           

          Can you please try this and let us know if you are able to see a consistent frame size?

           

          Best Regards,

          Jayakrishna