3 Replies Latest reply on Nov 23, 2020 4:30 AM by EktaN_26

    SPI slave DMA with WiFi transfer throughput issue

    EdPa_4705161

      Hi,

       

      I'm trying to use SPI slave DMA to receive a data from another device and transfer this data to PC via WiFi.

      But I found the throughput was not enough (about 2.58 KB/s).

      Could anyone help me to improve the performance?

       

      EVB: CYW9P62S1-43438EVB-01

      SDK: ModusToolbox_2.2.0.2801

       

      SPI configuration:

      2020-10-30_105444.jpg2020-10-30_105510.jpg

       

      DMA configuration:

      2020-10-30_105316.jpg

       

      Edgar

        • 1. Re: SPI slave DMA with WiFi transfer throughput issue
          EktaN_26

          Hi Edgar,

           

          Could you please provide your complete project archive?  The zip folder that you provided contains only the .c and .h files of the project.

           

          Best Regards

          Ekta

          • 2. Re: SPI slave DMA with WiFi transfer throughput issue
            EdPa_4705161

            Hi Ekta,

             

            I attached my complete project archive.

             

            Thank you for your help.

            Edgar

            • 3. Re: SPI slave DMA with WiFi transfer throughput issue
              EktaN_26

              Hello Edgar,

               

              Sorry for the delay in reply.

               

              There are a few things that you can try:

               

              1.The DMA runs on the clock_slow. In your design.modus the clock_slow is configured to work at a frequency of 50 Mhz. You can configure it to work at 100 Mhz. This can be done by changing the clock_peri divider in your project to 1.

               

              2. Increase the priority of the DMA0 to the highest by using the following "Cy_Prot_ConfigBusMaster(CPUSS_MS_ID_DW0, false, true, 0); function.

               

              3. You can also refer to the DMA Performance section in the Architecture TRM that mentions the number of clock cycles that would be required to complete a transfer. For a 1D transfer, the number of cycles required should be: 12+3*n+m, where n is the number of data elements to be transferred and m is the number of wait cycles.

              In your project n = 100 (in the attached image) so that should be 312 cycles considering m to be zero.

               

              The rest of the time that is being taken is occupied by the wait states.

               

              Please refer to this thread: What is the Maximum DMA Speed for a PSoC 6? which mentions in detail how to achieve maximum throughput in case of a DMA transfer.

               

              Best Regards

              Ekta