what are the clk_hf or clk_peri frequency, PERI divider for clk_scb, and CTRL.OVS setting in above cases? Thanks
Thanks for your reply. I'm using the following code to get the desired baud rates (9600bps to read ATR, and 115kbps after changing the PPS).
#define PERIPHERAL_SOURCE_CLK_FREQ 100000000 // 100MHz
#define OVERSAMPLING 16
#define MAX_VALUE_FRACTIONAL_BITS 32
uint32_t dividerValue = (PERIPHERAL_SOURCE_CLK_FREQ / OVERSAMPLING / bitrate) - 1;
uint32_t fracValue = (PERIPHERAL_SOURCE_CLK_FREQ / OVERSAMPLING % bitrate) * MAX_VALUE_FRACTIONAL_BITS / bitrate;
Using the above code:
# 9600 bps: dividerValue = 650, fracValue = 1
# 115200 bps: dividerValue = 53, fracValue = 8
1, how do you generate the PWM clock 3.57MHz?
I assume 3.57= 100/28
2, are you using internal IMO as clock source?
if so, there is some inaccuracy in the IMO source, maybe 2% (you may double check it).
3, there is some baud accuracy requirement for reliable UART communication.
the inaccuracy comes from clock source, dividers and OVS, and inaccuracy on the other side,
to debug the problem, I would propose to use integer divider (not fractional one, or set fractional part to 0).
you can calculate the divider caused inaccuracy in a Excel file, and find the best-fit integer divider value.
for 115.2Kbps case, could you try integer divider of 54?
1. I'm using this code block to set the PWM clock:
#define ISO7816_DEFAULT_PWM_CLK_FREQUENCY 3570000UL // 3.57MHz
#define PWM_DUTY_CYCLE (50.0f)
#define ISO7816_CLK (P6_3)
2. The UART clock source is CLK_PERI (100MHz +- 2.4%), as per default in Device Configurator
3. I have previously used Cy_SysClk_PeriphSetDivider(integer divider) and also ran into the same issue (unable to go beyond 38.4kbps).
Any other suggestion?
you can search article "Determining Clock Accuracy Requirements for UART Communications" for reference.
when eye window is 75% of bit time (depending signal quality), the clock accuracy requirement is about 3.3%.
at the first step, IMO clock source already take 2.4%,
at the second step, clk_scb divider will also cause some inaccuracy,
4, what is the card device? what is the max supported data rate?
5, do you have yet another read device? can it work at higher data rate?
6, the same hardware module worked well in pass ten years.
I have no more idea to debug now.
what is your location and end application?
you can create an CRM case when necessary, so the AE team can try to reproduce this issue and debug.
I have new findings. I have tried 3 configurations.
One of them is able to perform ISO7816 at 115kbps:
#define ISO7816_1_RESET (P6_3)
#define ISO7816_1_CLK (P6_0)
#define ISO7816_1_IO (P6_1)
Two of them failed (>= 38.4kbps)
#define ISO7816_2_RESET (P9_3)
#define ISO7816_2_CLK (P9_0)
#define ISO7816_2_IO (P9_1)
#define ISO7816_3_RESET (P5_7)
#define ISO7816_3_CLK (P5_4)
#define ISO7816_3_IO (P5_5)
I have experimented on two PSoC 6 Wi-Fi-BT Prototyping Kits, with different combinations of SIM slot hardware, getting the same outcome. I'm using are SIM cards, capable of reaching 230kbps (the ATR TA1 byte is 0x96). I would like to make a USB smart card reader with multiple ISO7816 slots.
Any idea what could be wrong with P5_5 and P9_1? Thanks!