4 Replies Latest reply on Nov 4, 2020 10:20 PM by MallikaK_41

    CY4533 EZ-PD schematic edit

    huab_867446

      Dears,

       

      Hope you are fine,

       

      Recently, we use the CY4533 EZ-PD schematic to support us with USB type C power stand alone configuration. However, we need to modify this schematic due to layout area considerations and BOM reduction as follows,

       

      • Delete Q1 and Q2 and connect VBUS to our product directly as shown in the following image, while our product has a snubber circuit at its input pin

      image.png

      • Unless the above solution is available, are we able to short the output of two FET rails (DC_out and SAFE_5V_OUT)?
      • Is there any timing constrain between VBUS_FET_EN and VSAFE5V_EN?

       

      Appreciate your fast response to help us find our way forward.

       

        • 1. Re: CY4533 EZ-PD schematic edit
          MallikaK_41

          Hi,

           

          The attached image cannot be opened.

          Can you please check and re-attach it?

           

          Best Regards,

          Mallika

          • 2. Re: CY4533 EZ-PD schematic edit
            MallikaK_41

            Hi,

             

            Q1 and Q2 are a set of back-to-back Power PMOSFETS. They have the following functions:

            a) Reduce inrush current due to large capacitive loads.

            b) When the VBUS input on the Type-C connector is out of range or if the attached Type-C power adapter cannot supply the voltage required by the system, the BCR device will turn the FETS off.

            So in short, they are important for enabling/disabling VBUS path.

             

            Regarding DC_OUT and SAFE_5V_OUT, the two outputs are different. DC_OUT is the output of the BCR board (can be from 5V to 20V depending upon the power ability of the adapter) while SAFE_5V_OUT is the default 5V provided when the Type-C power adapter cannot provide the voltage or current set in selector pins.

            When a suitable set of PDOs are not available , 5V default load switch turns on (BCR turns on FET through VSAFE5V_FET_EN) and VBUS falls back to 5V.

             

            Regards,

            Mallika

            • 3. Re: CY4533 EZ-PD schematic edit
              huab_867446

              Hi Mallikak,

               

              Thanks for your reply,

               

              Thanks for your clarification but I want to know the comments behind our edits if possible.

               

              unnamed.png

              • 4. Re: CY4533 EZ-PD schematic edit
                MallikaK_41

                Hi,

                 

                >> I would recommend you to use the FETS since it is the requirement of Power Delivery Specification.

                When PD contract is not established, the voltage of VBUS should be kept below Vsafe0V. Only when the PD contract is established, the FET gate could be open.

                CYPD3177 has two pins (VDC_OUT&VBUS_IN) to monitor the voltage before and after the FET gate. If there are no VBUS FETS, it may trigger over voltage protection because the voltage level on VDC_OUT should be zero before the VBUS FETS open.

                When the voltage on VBUS does not meet the expectation, the chip would not work as normal.

                 

                Best Regards,

                Mallika