Very interesting. I plan to try to reproduce this effect.
A few questions:
You said you originally had P2.1 configured as Open Drain. Drive High.
Was the LED on before going to low-power mode?
What was the logic state of P2.1 before going to low-power mode?
Theoretically it is possible that an LED (normally an output device) can act as a low-efficiency input device. This would be true since the LED requires a lens to amplify focus the light generated by the LED junction. This same lens could focus incoming light onto the junction allowing some electrons to cross the junction barrier creating a lower resistance in the presence of higher intensity light.
However to achieve this effect, the LED must have some positive voltage on the anode with respect to the cathode. When you reconfigure P2.1 to Strong or Pulldown with an output logic state at 0, if forces effectively 0V on the anode.
Here's a link to an article about using the LED as a photodetector: https://www.electronicdesign.com/markets/lighting/article/21777096/single-led-takes-on-both-lightemitting-and-detecting-…
A similar effect is known with speakers acting like a microphone. It is possible but not highly efficient.
Our application basically spends most of the time in sleep (CyPmSleep(PM_SLEEP_TIME_NONE, PM_SLEEP_SRC_CTW)), using the RTC_EverySecondHandler interrupt for wakeup. P2.1 is set low before sleep (initially floating in the Open drain, drive high mode). The component schematic for P2.1 actually shows an input buffer in all digital modes, I guess that indiciation really means business and leaving it floating during the sleep cycle apparently invokes this quirk.
This effect is NOT consistent for all CY8KIT-059 units, some have a pronounced effect while others have a much less pronounced effect!
To answer your questions:
'You said you originally had P2.1 configured as Open Drain. Drive High.'
'Was the LED on before going to low-power mode?'
No, P2.1 is always set low before calling CyPmSleep().
'What was the logic state of P2.1 before going to low-power mode?'
P2.1 is always set low before calling CyPmSleep() and the LED is off, I never thought to check it as an input...
This inconsistent quirk baffled us for a long time and we are perfectly satisfied and happy with the solution we found (Resistive pull up, drives high), I just wanted to let the community know in case others ran into the same quirk.
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I'm doing more research to verify this operational quirk.
The component schematic for P2.1 actually shows an input buffer in all digital modes, I guess that indication really means business and leaving it floating during the sleep cycle apparently invokes this quirk.
If this is true, I believe I have your answer why in Open drain, drives high mode this effect occurs. I've actually had this effect "bite me" on another non-Cypress product. It also explains why your two solutions work.
A Hi-Z digital input circuit looks like this:
Each FET (high-side and low-side) operates mostly in binary mode depending on the input gate voltage. Binary mode is either fully on (Rds<200 ohms) or fully off (Rds>1M ohms).
FETs have a linear region around the gate input switch-over voltage which is around VDD/2. This linear region is small but when in this region the Rds is somewhere between the fully on or fully off resistance. When BOTH FETs (hs and ls) are in the linear region, current flows between VDD and GND. This is the end effect you are seeing when the pin is configured as Open drain, drive high.
The second effect is that the LED is acting as a photo-galvanic generator like a solar cell element. It is essentially an energy harvesting device (an inefficient one) that is generating a voltage high enough to push the HiZ digital input circuit to go into linear mode depending on light intensity.
I learned this issue the hard way in a now retired design. In development, I found that the required sleep current of <100uA was not always occurring in the presence of a high RI (Radiated Immunity) fields. This is because the trace and external input circuit became an antenna for certain frequencies. At these resonant frequencies, the AC harmonics caused the HiZ input to go into linear mode drawing current beyond the required <100uA. The fix we chose to implement was to set the HiZ digital input to output set to logic 0 just before sleep. This shorted any potential RI transients in sleep mode with a low-impedance connection to GND.
I should note that these RI transients can still effect the input when not in sleep mode. It would have to be potentially addressed if in your application this could cause false action.