3 Replies Latest reply on Oct 21, 2020 9:26 AM by MiLe_2706411

    For S29JL064J design I have two questions.

    MiLe_2706411

      My company purchased several lots a material from Spansion of this device to provide customers in the Space market radiation screened devices.

       

      With that said, one of our customers has experience two separate incidents of data retention issue.

       

      Question 1) Is there any evidence that programming a device multiple times sequentially enhances programming cell margins?

       

      Question 2) Does Spansion/Cypress perform wakeup cycling on this type of technology or does characterization show that programming performance is enhanced after some number of initial new silicon programming cycles?

       

        • 1. Re: For S29JL064J design I have two questions.
          AlbertB_56

          Hello,

           

          Thank you for contacting Cypress Semiconductor.

           

          It is unclear as to the type data retention issue your end customers are encountering.  However, the answer to both of your questions is 'NO,'

           

          The average neutron and alpha SER for the Floating Gate Parallel NOR product family was observed to be <0.01 FIT/Mb.

           

          The JL064J ( 'J' = 110nM Floating Gate process technology) passed the Average SER FIT Rate of < 0.001 [FIT/Mb], as well as

          the Cypress Specs Target FIT Rate of < 0.001 [FIT/Mb].  

           

          The neutron SEL and SEU susceptibility was measured at the Los Alamos Neutron Science Center, LANSCE within the Los Alamos

          National Laboratory (LANL).  The Floating Gate Parallel NOR SER/SEL Reliability Report is company confidential and cannot be shared.

           

           

           

          Best regards

          Albert

          Cypress Semiconductor Corp

          An Infineon Technologies Company

          • 2. Re: For S29JL064J design I have two questions.
            AlbertB_56

            Hello,

             

            Thank you for contacting Cypress Semiconductor.

             

            It is unclear as to the type data retention issue your end customers are encountering.  However, the answer to both of your questions is 'NO,'

             

            The average neutron and alpha SER for the Floating Gate Parallel NOR product family was observed to be <0.01 FIT/Mb.

             

            The JL064J ( 'J' = 110nM Floating Gate process technology) passed the Average SER FIT Rate of < 0.001 [FIT/Mb], as well as

            the Cypress Specs Target FIT Rate of < 0.001 [FIT/Mb].  

             

            The neutron SEL and SEU susceptibility was measured at the Los Alamos Neutron Science Center, LANSCE within the Los Alamos

            National Laboratory (LANL).  The Floating Gate Parallel NOR SER/SEL Reliability Report is company confidential and cannot be shared.

             

             

             

            Best regards

            Albert

            Cypress Semiconductor Corp

            An Infineon Technologies Company

            • 3. Re: For S29JL064J design I have two questions.
              MiLe_2706411

              I appreciate your response.

               

              Our customer has experienced two devices that have had a single bit retention failure. This was two devices out of only a couple hundred as satellite applications tend to be low quantities.   Not sure if these are the more typical zero to ones retention failure caused by leakage on the floating gate. 

               

              I have experience as a product engineer with floating gate 350nm process for an EEPROM manufacturer.  We had a test mode whereby we could perform margin reads by sweeping the sense amp reference voltage to see how well the memory cells were programmed (erased or charged).  That technology for new wafers, did exhibit programming improvements after some numbers of wakeup cycling on initial silicon.  My followup questions are;

               

              How does temperature effect programming margins?  For example are programming margins  worst case at cold or hot temperature? 

               

              Does temperature effect read performance?

               

              Thank You,