The PSoC Creator would be correct (up to 50.4MHz), but it is necessary to confirm about datasheet notation.
I'll check them as soon as possible.
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The PLL IP itself in PSoC4L is capable of 104MHz as shown as the datasheet you suggested (001-91686 Rev. *J : SID414), but PLL legal rang is depending on each device.
Then it’s available the PLL range (min 22.5MHz and max 50.4MHz) in the PSoC4L device.
It is timing closed at a much lower frequency, so it is not allowed to run the PLL output above 50.4 MHz as PSoC4L device.
So the PLL IP block spec doesn't apply for max frequency and the chip spec (min 22.5MHz and max 50.4MHz) is applied in PSoC Creator.
Thank you for your answer.
I understand the contents.
In that case, it would be nice if the data sheet had annotations.