The WDT block is sourced from ILO (CTW - 1Khz) which has an accuracy of -50 to +100 %. Therefore you find this inaccuracy range in the WDT interval. From the system reference guide and architecture TRM, when WDT is configured to CYWDT_128_TICKS, it is expected to have periods range at 256 – 384 ms.
Was there any specific event that caused this period to change?
To improve accuracy you can use the ILO trim component, details of which can be found at the following links:
https://www.cypress.com/documentation/code-examples/ce95328-1khz-ilo-trimming-psoc-35lp - Use PSoC Creator to get latest version of this example. (File > Code example)
Thanks for the quick reply.I did not know that it was so imprecise.
Does this mean that each device can have different Trim settings?
It doesn't seem like a good solution.