4 Replies Latest reply on Oct 15, 2020 2:49 PM by AlbertB_56

    State of SPI bus during power off (CYPT16B512)

    chco_2244511

      Hi,

       

      I would like to connect 2 serial flash CYPT16B512 on the same SPI bus. Only one device will be powered at any time. I would like to know what is the state of the SPI bus on the CYPT16B512 device when the power is OFF. It is not clear from the datasheet, the state of the SPI bus is marked as 'X'. Is there some protection diode internally that will force the bus to a low state?

       

      Regards,
      Christophe

        • 1. Re: State of SPI bus during power off (CYPT16B512)
          AlbertB_56

          Hello Christophe,

           

          Thank you for contacting Cypress Semiconductor.

           

          When the CS# signal on the CYPT16B512 is at the logic high state, the device is not selected and all input signals are ignored and all output signals are high impedance. Unless an internal Program, Erase or Write Registers (WRR) embedded operation is in progress, the device will be in the Standby Power mode. Driving the CS# input to logic low state enables the device, placing it in the Active Power mode. After Power-up, a falling edge on CS# is required prior to the start of any command.  Therefore, there should be no influence from the device that is

          de-selected or powered off.

           

           

           

          Best regards,

          Albert
          Cypress Semiconductor Corp

          An Infineon Technologies Company

          • 2. Re: State of SPI bus during power off (CYPT16B512)
            AlbertB_56

            Hello Christophe,

             

            Thank you for contacting Cypress Semiconductor.

             

            When the CS# signal on the CYPT16B512 is at the logic high state, the device is not selected and all input signals are ignored and all output signals are high impedance. Unless an internal Program, Erase or Write Registers (WRR) embedded operation is in progress, the device will be in the Standby Power mode. Driving the CS# input to logic low state enables the device, placing it in the Active Power mode. After Power-up, a falling edge on CS# is required prior to the start of any command.  Therefore, there should be no influence from the device that is

            de-selected or powered off.

             

             

             

            Best regards,

            Albert
            Cypress Semiconductor Corp

            An Infineon Technologies Company

            • 3. Re: State of SPI bus during power off (CYPT16B512)
              chco_2244511

              Thanks Albert  for the prompt feedback.i will then implement this configuration where both devices are on the same bus. I just want to add that both devices will have the same CS#. The selection is done by powering only one device at any time.

               

              Regards,
              Christophe

              • 4. Re: State of SPI bus during power off (CYPT16B512)
                AlbertB_56

                Hi Christophe,

                 

                Yes, even with both devices sharing CS#, when VCC is removed from one of the CYPT16B512, both the inputs and outputs are essentially off.  Any commands sent to the CYPT16B512 (with VCC off) will be ignored, and obviously no data will be outputted.

                 

                 

                 

                Best regards,

                Albert

                Cypress Semiconductor Corp

                An Infineon Technologies Company