P.s. I believe the number of data words that it writen by DR_DATA is coupled to the USB endpoint size, which gives this limitation. For max. transfer speed, this is set to the max, which is 1024 bytes. Lowering the USB endpoint size might be the solution, but it would lower the performance significantly (my guess).
If you are using a synchronous interface between FX3 GPIF II block and FPGA, then one DR_DATA action will drive an amount of data that is equal to the GPIF II bus width only in one clock cycle and not 1024 bytes.
As per my understanding, you want to configure FPGA using FX3 through GPIF II interface. The configuration data will be obtained from the USB host. Also, FX3 state machine should monitor a READY signal issued by the FPGA. If the READY signal is de-asserted, then FX3 should send not more than 6 words of data. Please correct me if Iam wrong.
For this, you can modify the state machine that comes along with Application Note AN87216. The link to the same is given below:
After downloading the project files, the master state machine can be found in the following location:
..\Master interface-AN87216\AN87216 Source Files\GPIF II Projects\master_read_write_sync.cydsn
Please refer to the Application Note and the state machine to understand the functionality better. After this, you can modify the GPIF Designer project for fulfilling your requirements. For this, from the state where DR_DATA is called, use a transition equation to another state (say DE_ASSERT) using the transition equation !READY (which comes from FPGA). In DE_ASSERT state, a counter should be implemented and DR_DATA should also be done.
As you might know, there are 3 counters available with the GPIF state machines. They are DATA_COUNT, ADDR_COUNT and CTRL_COUNT. You can load the count values by using the actions LD_DATA_COUNT, LD_ADDR_COUNT and LD_CTRL_COUNT. The counter values can be incremented by using COUNT_DATA, COUNT_ADDR and COUNT_CTRL respectively. You can use one counter for your requirement (say data counter) and configure it to count till 6. You can use DR_DATA until it reach 6. When the count reaches 6, the transition equation DATA_CNT_HIT will become true. Use this transition equation to jump to an IDLE state(where nothing is done).
Now, the state machine can undergo a transition from the IDLE state to the first state where DR_DATA is done with the transition equation READY. Please note that I have suggested these state transition equations on the assumption that asserting READY signal by FPGA makes it HIGH and de-assertion makes it LOW. It may change based on how you have set the FPGA.
Please let me know if you have any questions on this.
Thank you for the quick reply.
This part answers my question perfectly "then one DR_DATA action will drive an amount of data that is equal to the GPIF II bus width only in one clock cycle and not 1024 bytes."
That's perfect, I didn't know. I have used the GPIF II designer before for multiple designs and so far I have been using the counter "wrong", as I always worked with bursts of 1024 bytes, while this is not necessary.