Hmm. On the PSoC5 there is the DataPath which routes digital signals and there is the analog routing 'fabric'.
By assigning the input to digital in TopDesign, Cypress routes it to the PWM component.
By reassigning the input in SW to analog, you have effectively cut this path. Is this what you desire?
Did you know that the input can be assigned at digital and analog input at the same time in TopDesign?
I know that the input can be analog input or digital input.
As a background to this question, PSoC5LP uses Hibernate mode.
The unused GPIO is set to Hi-Z to suppress the current consumption.
I am having a problem with the operation of PSoC5LP and reviewing the software.
Analog, digital input and digital output were also set to Analog Hi-Z.
It seems that there is no problem in operation, but I would like to know if something could go wrong.
It seems that I referred to the following of AN77900.
As a treatment for unused pins (during hibanating?).
Of course, I also understand that It need to change to digital Hi-Z(DM_DIG_HIZ) instead of analog Hi-Z(PIN_DM_ALG_HIZ).
There is a transmission gate that is enabled when you switch the mode... what I dont know is what the output side of the transmission gate is attached to inside of the chip... I suspect that the answer is nothing... meaning it is unattached.... and the reason we put that in the datasheet it that is the lowest power configuration.
I think I understand better your intention.
Just before you go into hibernation, I recommend changing your HiZ-digital to HiZ-analog. Here's the reason why:
I had a project many years ago where an input was set to HiZ-digital for use in the application. If was based by a switched VDD.
In low-power mode (LPM), I was required to target < 100uA. When I went into LPM, the sleep current was about 64uA ... until the switched VDD bias that was switched off just before sleep drops to about 1/2 VDD. At that point the HiZ-digital input went into linear mode and the sleep went to >200uA for about 10 seconds until the bias voltage dropped below the linear input range where it returned to 64uA.
To fix it, I set the input HiZ-digital to HiZ-analog before sleep.
Hope this helps.
Since you haven't shared your input circuit with the forum it is hard to infer better conclusions.
PS: One more caveat. What is the impedance of your input circuit?
The reason I ask is historically with the company I worked for, we would have to keep the circuit impedance to 100K ohms or lower.
The reason for this is that a high impedance circuit with circuit traces can be prone to oscillations in the influence of high electric/magnetic fields. With an input as HiZ=digital it could be possible that the oscillations would cross the input switching threshold many times causing undesired effects such as excess sleep current or unintentional wake up.
A HiZ-analog should not be prone to this issue. However, I better solution in some cases is to turn the input to an output with a 1 or 0.
In PSoC 5LP Architecture TRM 001-78426 Rev.*G, 19. I/O System
I found following diagrams and tables.
I visited this chapter when I wanted to change I2C pins to GPIO so that I can force reset the bus.
(1) GPIO Block Diagram
(2) I/O Drive Modes
(3) Drive Mode Diagrams
To save power, setting the drive mode to High Impedance should be ok,
but IMHO, since you are connecting the pin to the enable of PWM component,
I may want to try High Impedance Digital, instead.
Thank you everybody.
Since I had CY8CKIT-059, I tried PWM and Digital Input pins as examples.
In fact, GPIOs such as UDB also change from Digital Input/Output to Analog Hi-z before entering Hibernate mode.
I thought there was no problem because it was Analog Hi-Z when the power was turned on.
But it is difficult to handle Digiral Hi-Z and Analog Hi-Z.
Perhaps the problem I'm facing has other causes.
There are only two power modes where the UDBs are powered: Active and Low Power.
Other power modes such as Sleep, Deep Sleep and Hibernation, the power is removed from the UDBs. That is why there are API calls specifically to save and restore the UDB configuration of the component before and after low power mode. (PWM_SaveConfig() and PWM_RestoreConfig()).
We could use both of Analog and Digital on a GPIO.
So you can use High Z analog drive mode on digital pin.
High Z analog drive mode should be used for any pin connected to any analog component.
About details above, there are in a section 6.10 “Using both Analog and Digital on a GPIO” of AN86439 PSoC® 4 – Using GPIO Pins
Also it could be used for digital pin to save power consumption at once during a device is on sleep mode, as Len said.
I believe it’s used for this case at this time.
But in this case, it’s must be changed a drive mode back for GPIO pin (Strong drive mode etc.) when it’s used again after wake-up.
Please make sure them.