No, such tool doesn't exist.
Note that PSoC5 has very limited PLD space, so whatever code you want to port it has to be small. In that case, it can be easily ported manually.
thank you, if I send to you the vhdl source file could you verify if could be fit into PLD and try to translate it?
I have no experience with VHDL. The best would be posting the code and description here on the forum, so it can get maximum attention.
There was software to convert from VHDL to Verilog.
VHDL to Verilog Transfer software URL
After converting VHDL to Verilog,
You can refer to the Component Author Guide to create custom components.
Component Author Guide URL
PLDs of PSoC are small.
Please check the scale from the table below.
Especially when the number of terms is large, the PLD of PSoC is easily restricted.
thank you for you reply.
At the moment I'm using my VHDL component into a FPGA, but I'm wondering if I could move it to a PSoC5LP.
On the datasheet of the component it indicates that the used resource are 6000 logic gate.
Do you think it could be fit or not on a PSoC5LP? If not, I do not try to translate it as Verilog...
Thanks and regards
Direct migration of VHDL/Verilog code is typically not the most efficient way as the synthesis tools are not smart enough to reuse the UDB blocks, which could be seen as micro-ALU with FIFOs. So to above question the answer would be no, unless you redesign and reuse the UDB. So in PSoC think rather from UDB surrounded by the logic, then you can squeeze out really a lot.
I think the 6000 gates are difficult with the PLDs(12C4) in the UDB block alone.
Of course, it depends on the contents of the VHDL language such as the number of bits of variables to be handled, the number of IO (Terms) and parallel processing.
As BR Uros-san says, I think it's tough if you don't make full use of the data path(8bit ALU).
Moreover, the design of the data path is very complicated.
It would be easier to tell us what exactly you want to implement with PSoC 5LP. Maybe someone else already implemented the same functionality leveraging the UDBs.
What does your VHDL component do?
My component is a little bit complicated since I have no experience with VHDL.
For the moment I think I can not fit into PSoC5LP since I have to include also other logic..