With the timers working better, I was able to run an experiment that suggests Cy_MCDWDT_SetInterrupt actually triggers the interrupt.
The Cy_MCWDT_SetInterruptMask() function writes to the Multi-Counter Watchdog Counter Interrupt Mask Register. You can refer to this Register details in the PSoC 6 Register TRM. The Interrupt Mask Register has control bits for each of the counters. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1.
The Cy_MCWDT_SetInterrupt() function writes to the Multi-Counter Watchdog Counter Interrupt Set Register (see page 609 of PSoC 6 Architecture TRM). It sets MCWDT interrupt sources in the interrupt request register. This register has three bits (0,1 and 2) to set interrupt for MCWDT_INT0, MCWDT_INT1 and MCWDT_INT2 respectively.
I always found this confusing as well... and in fact almost always need to look it up in the register Which is what I did this morning... again (you would think that I would learn).
There are three interrupt registers per TCPWM counter (remember each TCPWM block has multiple counters)
All three of the above registers have two bits.
TC = Terminal Count
CC = Compare
When the CC or TC event happens in the hardware, the corresponding bit is set to 1 in the TCPWM_CNT_INTR register. To clear an interrupt you need to write a 1 into the corresponding bit of this register (yes a 1 turns the bit to 0)
If for some reason you want to set (means turn a bit to 1) the TCPWM_CNT_INTR register from software, you need to do that by writing the TCPWM_CNT_INTR_SET register.
There is only 1 interrupt line going to the NVIC for each counter. That line is the result of the TC or CC condition AND the coresponding mask.
interrupt = (TCPWM_CNT_INTR.TC & TCPWM_CNT_INTR_MASKED.TC) | (TCPWM_CNT_INTR.CC & TCPWM_CNT_INTR_MASKED.CC)
In other words and interrupt to the CPU will happen when the condition is met (either TC or CC) AND that interrupt is Masked ON (the corresponding bit is set in the mask register)
You don't need to write any of these bits directly as we provide PDL for you.
- reads TCPWM_CNT_INTR register (two bits)
- writes 1 (which clears the interrupt) into TCPWM_CNTR_INTR reguster
- writes 1 into TCPWM_CNTR_INTR_SET register (which then sets the bit in the TCPM_CNTR_INTR register)... this is a software trigger of the interrupt
These functions read write TCPWM_CNTR_INTR_MASK
Essentially enabling the interrupt to go through to the NVIC
- this reads TCPWM_CNT_INTR_MASKED register
- this = TCPWM_CNT_INTR & TCPWM_CNTR_INTR_MASK
- the or of the two TC/CC bits is what goes through to the NVIC
The question was about the MCWDT not the TCPWM (my last question was, though). Nevertheless, I think what you are saying applies mostly to the MCWDT except I believe an interrupt fires only for a match.
Thanks EktaN_26. I read the TRM for the architecture and for the registers. What I still don't quite get is what an Interrupt source is. Does the source enable the interrupt and the mask all the interrupt to come through. As I stated in my own reply above, calling that function appeared to cause the interrupt to fire immediately.
The PSoC 6 MCU supports 147 interrupts from peripherals. The source of each interrupt is listed in Table 8-3 of the Architecture TRM.
You would see in the table that System Interrupt (IRQ19) is the Multi-Counter Watchdog Timer (MCWDT0) Interrupt.
This interrupt will be triggered when you call the Cy_MCWDT_SetInterrupt() function. The source of the interrupt will be one of the counter 0,1 or 2 based on the parameter you pass in the function.