6 Replies Latest reply on Oct 15, 2020 11:58 AM by BoTa_264741

    comparator bypass mode

    user_3716231

      I have some questions about comparator bypass mode and I marked the sentence that I don't understand.

      1. Is it mean "the output is neither synchronized with bus clock on rising edge nor synchronized to the bus clock on falling edge" or "the output is not synchronized with bus clock on rising edge but it synchronized to the bus clock on falling edge"?

      clock input.PNG

       

      2. What is that mean reset comparator output?Why reset it?

      sync.PNG

        • 1. Re: comparator bypass mode
          BoTa_264741

          User_371..,

          1. I believe that in bypass mode "the output is not synchronized with bus clock on rising edge but it is synchronized to the bus clock on falling edge".

           

          2. The "reset" here means comparator output going low when input conditions ( +) < (-).

          /odissey1

          • 2. Re: comparator bypass mode
            VasanthR_91

            Hi,

             

            Confirming the answers by /odissey are right.

             

            1,The output is synchronized with bus clock on rising edge [corrected]

             

            2. It means comparator output going low.

             

            Best Regards,

            Vasanth

            • 3. Re: comparator bypass mode
              user_3716231

              So,when comparator set to bypass mode,the output(no matter it is going low or high) is synchronized to the bus clock on falling edge ,right?

              If it is true,why do second sentence say the output set(going high) immdiately and reset(going low) on rising edge of the bus clock?

              • 4. Re: comparator bypass mode
                BoTa_264741

                user_371...,

                No, that's incorrect. When comparator is in bypass mode, the output goes  High instantly if conditions > are met, and it waits for the next rising edge of the BUS_CLK to set its output Low when conditions < are met.

                 

                In short, it behaves like a D-flip-flop with asynchronous set a synchronous reset.

                /odissey1

                • 5. Re: comparator bypass mode
                  user_3716231

                  But the first sentence means the output is synchronized to the bus clock on falling edge.

                  the second one means the output going high immdiately when > and going low when < on the next rising edge of the bus clock.

                  It seems they are conflicted to each other.

                  • 6. Re: comparator bypass mode
                    VasanthR_91

                    Hi

                     

                    There was in inaccuracy in the documentation and the first response. I had to do some digging to find the right answer.

                     

                    In bypass mode the output  of raw comparator output is captured with an asynchronous set / synchronous clear flop. It is triggered on bus clock. Additionally it will be best to use the normal mode of the comparator as a suggestion.

                     

                    We will do necessary steps to correct the documentation.

                     

                    Best Regards,
                    Vasanth