1. I believe that in bypass mode "the output is not synchronized with bus clock on rising edge but it is synchronized to the bus clock on falling edge".
2. The "reset" here means comparator output going low when input conditions ( +) < (-).
Confirming the answers by /odissey are right.
1,The output is synchronized with bus clock on rising edge [corrected]
2. It means comparator output going low.
So,when comparator set to bypass mode,the output(no matter it is going low or high) is synchronized to the bus clock on falling edge ,right?
If it is true,why do second sentence say the output set(going high) immdiately and reset(going low) on rising edge of the bus clock?
No, that's incorrect. When comparator is in bypass mode, the output goes High instantly if conditions > are met, and it waits for the next rising edge of the BUS_CLK to set its output Low when conditions < are met.
In short, it behaves like a D-flip-flop with asynchronous set a synchronous reset.
But the first sentence means the output is synchronized to the bus clock on falling edge.
the second one means the output going high immdiately when > and going low when < on the next rising edge of the bus clock.
It seems they are conflicted to each other.
There was in inaccuracy in the documentation and the first response. I had to do some digging to find the right answer.
In bypass mode the output of raw comparator output is captured with an asynchronous set / synchronous clear flop. It is triggered on bus clock. Additionally it will be best to use the normal mode of the comparator as a suggestion.
We will do necessary steps to correct the documentation.