Could you share more details about the project ? DMA configuration code and details might be helpful. You can share you code using PSoC Creator -> File -> Create Workspace bundle(minimal).
- You are using the same sine wave table (SWT) for both waveforms in VDAC1 and VDAC2.
- Your SWT has 128 points.
The issue you are having is the DDS24 with two outputs are clocked at the same frequency to be the source of the DMA for the VDACs. Therefore, ONE sine wave is accomplished using 128 DDS24 DMA requests.
The phase shift you introduced into the DDS24 out2 phase shifts the sine wave output of the second wave by at most 1/128th of 360 degrees (2.81 degs) at most.
Here are some ideas to address your issue. In each idea, there is NO need to use the DDS24 phase shift.
Idea #1 - Two SWTs
This is BoTa's (/odissey1) idea. Create 2 SWTs with the second table starting with the sine wave phase shift you desire. The downside is that the second table (in RAM) needs to be recomputed when you want to adjust the phase on-the-fly.
Idea #2 - Same SWT, different DMA starting point.
Create a single SWT for both VDAC1 and VDAC2. You can use a different DMA starting point in the SWT for each waveform. The starting point of VDAC2 will determine the phase of the sine. This can be done by defining the first TD for the second wave to a different starting index and length. The next TD points to the entire waveform and the length to all the points. The potential downside of this method is that the second wave will most like not start at 0V amplitude. Depending on your application, this might be an issue.
Example. If you want a 180 deg phase delay: VDAC1 starts at index = 0 and VDAC2 starts at index = <max/2>
Idea #3 - Same SWT, Enable the 2nd wave with a time delay
Create a single SWT for both VDAC1 and VDAC2. Start the DDS24 with out1 enabled and out2 disabled. After a time delay computed for required phase delay for VDAC2, enable out2. This will start the DMA sequencing for VDAC2 at the desired sine wave phase delay. Note: The second wave is started at 0V.
Downside: At this time, there is no HW enable for out2 alone. There is an API call for a SW enable and a HW clock enable to the entire DDS24 both out1 and out2.
To accomplish this idea, you would either need:
- An AND gate between out2 and the DMA. The AND gate would be controlled by a time-delayed signal for the second input. This HW time-delay could be a one-shot 8-bit timer with a variable period. (Since you have a SWT of 128 points you need an 8-bit with a period of up to 127). You can use out1 as the clock for your timer delay. This will strategy will give you 360/128 = +2.81 degs resolution of phase shift.
If you want more resolution, you can control the out2 phase delay to provide additional delay within the 2.81 degs max provided by the DDS24.
Note: If you ask BoTa nicely, maybe he'll consider adding the AND gate into out2 and a out2_en pin to control it.
- Two DDS24s where each can be controlled (and started) separately. With this method you can have more available resolution of the phase shift between waveforms.
Do you need some additional assistance with your issue?
Of the ideas I presented above, is there one that appeals to you?
If you are willing to share your project, I can help to modify it based on one of the ideas.
I think i accidentally created two forum posts where one was already answered before.
I implemented the same SWT but different starting points method. Thats your idea 2. Thanks for all your help