5 Replies Latest reply on Oct 4, 2020 2:57 AM by BoTa_264741

    PSoC5LP Gnerating Sine Waves with arbitrary Phase Shifts

    keko_4647076

      Hi, I am trying to build a system where I can can create two sine waves with arbitrary Phase shifts, which i can control in the code. I am using the DDS24 component created byBoTa_264741 as a clock source for the DMAs which will send the sine wave table data to the VDAC. The DDS24 component works well, but i am confused as why using the phase shifted signal from the DDS24 to send requests to the DMA which will then send data to the VDAC will not result in a phase shift in the output of the VDAC. Any guidance on what i am doing/thinking wrong is greatly appreciated. I have attached a photo of the DDS24 output, VDAC output and the schematic.

      Capture.PNG

        • 1. Re: PSoC5LP Gnerating Sine Waves with arbitrary Phase Shifts
          BoTa_264741

          keko,

          I will take a look over weekend for a solution. Basically, you have to make 2 arrays in RAM (or single 2-byte array), and transfer sine data to VDAC_1 and VDAC_2 synchronously. To have phase shifted output, you need to override data in array 2 to be phase shifted against array 1.

           

          Please take a look on the demo project here

          Re: How do I change the phase of a sine wave generated by a DMA?

          /odissey1

          • 2. Re: PSoC5LP Gnerating Sine Waves with arbitrary Phase Shifts
            keko_4647076

            Hi BoTa_264741 Thanks , i will have a look at that. My goal is to easily change the phase of the sine wave using software. The phase will be calculated dynamically in the code. In addition i want to be able to change the frequency and amplitude, which i am doing using the DDS24 and multiplying the sine data table fed to the DMA.

             

            So my thinking is that if i change the phase of the clock signal fed in to the DMA, that the sine wave generated will also have the same phase shift as the clock signal, but this is not happening in my design. I am not sure if i am thinking correctly or i am missing something important.

             

            Thank you for your support

            • 3. Re: PSoC5LP Gnerating Sine Waves with arbitrary Phase Shifts
              BoTa_264741

              keko,

              The DDS24 has 2 outputs: primary NCO output and secondary phase shifted to the primary. To generate, say, 1 kHz, sine using 256-entry table, DDS should produce 256 kHz clock on the primary output, which corresponds to approx 4 us period. At say, 90 deg phase shift the secondary DDS output will be delayed against the primary by 1 us. So all it does is delaying each DMA_2 transfer by 1 usec, which is very fine and practically not visible on the sine2 wave. To achieve 90 deg phase shift between sine1 and sine2 waveforms, you need 250 usec.

               

              The link to the project provided above shows simplest way to achieve two synchronized sine outputs with phase shift and amplitude. Basically, DMA synchronously transfer data from the RAM multidimensional buffer. It is up to the user to populate the buffer with any sine data, including amplitude and phase. So every time you want to update amplitude or phase, you have to recalculate values in the buffer.

               

              What is frequency range are you targeting?

              /odissey1

              • 4. Re: PSoC5LP Gnerating Sine Waves with arbitrary Phase Shifts
                BoTa_264741

                keko,

                Another way could be is to start DMA_2 with some delay, corresponding to the phase shift necessary. To update the phase, one has to stop and reset all DMAs and DDS and start the process again. The drawback of this approach is that if some DMA transfers were skipped, the phase relationship will be lost forever. Unfortunately, DMA is prone to skipping tasks at high loads (>10MHz aggregate rate). For example, this phenomenon limits max sine output to Fmax ~17kHz (single channel):

                Fmax = BUS_CLK / DMA_clocks_per_transfer / sine_table_size =  48 MHz / 11 / 256 = 17 kHz

                • 5. Re: PSoC5LP Gnerating Sine Waves with arbitrary Phase Shifts
                  keko_4647076

                  Hi BoTa_264741 Thank you very much for all the answers, The maximum frequency i am targeting is 4kHz. I finally understand why my approach was wrong after you have explained it to me. I will try out the two solutions you have mentioned