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The Clock Synchronization and Routed Clock Implementation sections in page number 20 of the PSoC 4 System reference guide(link given below) might help you. Please go through it.
I tried with CY8CKIT-062-BLE.
Although this seems to be a little bit stupid, the phase seems to be reasonable.
Yellow is div2 (Pin_1), Red is dev8 signal (Pin_2).
thanks for looking into this. However, Ganesh put me on the right track, referring me to The Clock Synchronization and Routed Clock Implementation https://www.cypress.com/file/185351/download, and page 24 gave me the solution. Apparently the q output signal from the flip flop is synchronized with the provided clock signal, which means that each result is being offset with 1 clock cycle of the driving clock. The simplest solution is to tag each q result as asynchronous, using the UDB clock enable:
Just make sure the ClockOutSync setting is unchecked to indicate that the signal is asynchronous.
The datasheet of the Toggle Flip flop does not make any mentioning of this. The output now looks as expected. Only when zooming in, a delay of about 4ns between rising flanks (between each signal) could be detected, which is within spec.