5 Replies Latest reply on Sep 30, 2020 3:36 PM by NoTa_4591161

    Cascaded flip flops out of phase?

    Pava_1191361

      I need a number of frequencies that are in phase, based on a clock frequency. In Psoc-6 this should be possible by simply cascading a number of toggle Flip Flops:

       

       

       

      When simulated the signals are (as expected) in synch, as the output of one flip flop acts as source for the other flip flop:

       

       

      However, when I measured the output on pin P1_2, P1_3 and P1_4, the output is NOT is synchronized:

       

       

       

      It almost seems that P1_3 is triggered on the negative edge, in stead of the positive one, and P1_4 displays an unexpected phase shift related to P1_3. I had the same experience using D-Flipflops.

      What is happening, and what can be done to synchronize these signals?