I don't work for Cypress. My experience is that a soft error rate usually applies to dynamic RAM. PSoC's RAM is static. If there is a "soft error rate" it should be << 1ppb (sub 1 parts per billion). The FLASH and EEPROM have a 20 years retention and the FLASH has a minimum 10K cycle write endurance and the EEPROM a minimum 100K write cycle endurance.
This time, we are considering using PSoC5LP in an uninterruptible system.
Therefore, we are considering the effects of soft errors on SRAM of PSoC5LP.
SRAM with MCU has a small capacity, but since ECC is not installed,
We are guessing that the error rate is probably high.
This time, we will consider the value of non ECC SRAM of the 130nm process as a reference.
Cypress would have to weigh in as to how reliable their RAM is.
I've found over my years of experience that SRAM is VERY stable and reliable as long as the VDDD supplying it doesn't drop near the logic reset voltage.